1 /* 2 * (C) Copyright 2006-2007 Freescale Semiconductor, Inc. 3 * 4 * (C) Copyright 2006 5 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 6 * 7 * Copyright (C) 2004-2006 Freescale Semiconductor, Inc. 8 * (C) Copyright 2003 Motorola Inc. 9 * Xianghua Xiao (X.Xiao@motorola.com) 10 * 11 * See file CREDITS for list of people who contributed to this 12 * project. 13 * 14 * This program is free software; you can redistribute it and/or 15 * modify it under the terms of the GNU General Public License as 16 * published by the Free Software Foundation; either version 2 of 17 * the License, or (at your option) any later version. 18 * 19 * This program is distributed in the hope that it will be useful, 20 * but WITHOUT ANY WARRANTY; without even the implied warranty of 21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 22 * GNU General Public License for more details. 23 * 24 * You should have received a copy of the GNU General Public License 25 * along with this program; if not, write to the Free Software 26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 27 * MA 02111-1307 USA 28 */ 29 30 #include <common.h> 31 #include <asm/processor.h> 32 #include <asm/io.h> 33 #include <i2c.h> 34 #include <spd.h> 35 #include <asm/mmu.h> 36 #include <spd_sdram.h> 37 38 DECLARE_GLOBAL_DATA_PTR; 39 40 void board_add_ram_info(int use_default) 41 { 42 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; 43 volatile ddr83xx_t *ddr = &immap->ddr; 44 char buf[32]; 45 46 printf(" (DDR%d", ((ddr->sdram_cfg & SDRAM_CFG_SDRAM_TYPE_MASK) 47 >> SDRAM_CFG_SDRAM_TYPE_SHIFT) - 1); 48 49 if (ddr->sdram_cfg & SDRAM_CFG_32_BE) 50 puts(", 32-bit"); 51 else 52 puts(", 64-bit"); 53 54 if (ddr->sdram_cfg & SDRAM_CFG_ECC_EN) 55 puts(", ECC on"); 56 else 57 puts(", ECC off"); 58 59 printf(", %s MHz)", strmhz(buf, gd->mem_clk)); 60 61 #if defined(CONFIG_SYS_LB_SDRAM) && defined(CONFIG_SYS_LBC_SDRAM_SIZE) 62 puts("\nSDRAM: "); 63 print_size (CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024, " (local bus)"); 64 #endif 65 } 66 67 #ifdef CONFIG_SPD_EEPROM 68 #ifndef CONFIG_SYS_READ_SPD 69 #define CONFIG_SYS_READ_SPD i2c_read 70 #endif 71 #ifndef SPD_EEPROM_OFFSET 72 #define SPD_EEPROM_OFFSET 0 73 #endif 74 #ifndef SPD_EEPROM_ADDR_LEN 75 #define SPD_EEPROM_ADDR_LEN 1 76 #endif 77 78 /* 79 * Convert picoseconds into clock cycles (rounding up if needed). 80 */ 81 int 82 picos_to_clk(int picos) 83 { 84 unsigned int mem_bus_clk; 85 int clks; 86 87 mem_bus_clk = gd->mem_clk >> 1; 88 clks = picos / (1000000000 / (mem_bus_clk / 1000)); 89 if (picos % (1000000000 / (mem_bus_clk / 1000)) != 0) 90 clks++; 91 92 return clks; 93 } 94 95 unsigned int banksize(unsigned char row_dens) 96 { 97 return ((row_dens >> 2) | ((row_dens & 3) << 6)) << 24; 98 } 99 100 int read_spd(uint addr) 101 { 102 return ((int) addr); 103 } 104 105 #undef SPD_DEBUG 106 #ifdef SPD_DEBUG 107 static void spd_debug(spd_eeprom_t *spd) 108 { 109 printf ("\nDIMM type: %-18.18s\n", spd->mpart); 110 printf ("SPD size: %d\n", spd->info_size); 111 printf ("EEPROM size: %d\n", 1 << spd->chip_size); 112 printf ("Memory type: %d\n", spd->mem_type); 113 printf ("Row addr: %d\n", spd->nrow_addr); 114 printf ("Column addr: %d\n", spd->ncol_addr); 115 printf ("# of rows: %d\n", spd->nrows); 116 printf ("Row density: %d\n", spd->row_dens); 117 printf ("# of banks: %d\n", spd->nbanks); 118 printf ("Data width: %d\n", 119 256 * spd->dataw_msb + spd->dataw_lsb); 120 printf ("Chip width: %d\n", spd->primw); 121 printf ("Refresh rate: %02X\n", spd->refresh); 122 printf ("CAS latencies: %02X\n", spd->cas_lat); 123 printf ("Write latencies: %02X\n", spd->write_lat); 124 printf ("tRP: %d\n", spd->trp); 125 printf ("tRCD: %d\n", spd->trcd); 126 printf ("\n"); 127 } 128 #endif /* SPD_DEBUG */ 129 130 long int spd_sdram() 131 { 132 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; 133 volatile ddr83xx_t *ddr = &immap->ddr; 134 volatile law83xx_t *ecm = &immap->sysconf.ddrlaw[0]; 135 spd_eeprom_t spd; 136 unsigned int n_ranks; 137 unsigned int odt_rd_cfg, odt_wr_cfg; 138 unsigned char twr_clk, twtr_clk; 139 unsigned int sdram_type; 140 unsigned int memsize; 141 unsigned int law_size; 142 unsigned char caslat, caslat_ctrl; 143 unsigned int trfc, trfc_clk, trfc_low, trfc_high; 144 unsigned int trcd_clk, trtp_clk; 145 unsigned char cke_min_clk; 146 unsigned char add_lat, wr_lat; 147 unsigned char wr_data_delay; 148 unsigned char four_act; 149 unsigned char cpo; 150 unsigned char burstlen; 151 unsigned char odt_cfg, mode_odt_enable; 152 unsigned int max_bus_clk; 153 unsigned int max_data_rate, effective_data_rate; 154 unsigned int ddrc_clk; 155 unsigned int refresh_clk; 156 unsigned int sdram_cfg; 157 unsigned int ddrc_ecc_enable; 158 unsigned int pvr = get_pvr(); 159 160 /* 161 * First disable the memory controller (could be enabled 162 * by the debugger) 163 */ 164 clrsetbits_be32(&ddr->sdram_cfg, SDRAM_CFG_MEM_EN, 0); 165 sync(); 166 isync(); 167 168 /* Read SPD parameters with I2C */ 169 CONFIG_SYS_READ_SPD(SPD_EEPROM_ADDRESS, SPD_EEPROM_OFFSET, 170 SPD_EEPROM_ADDR_LEN, (uchar *) &spd, sizeof(spd)); 171 #ifdef SPD_DEBUG 172 spd_debug(&spd); 173 #endif 174 /* Check the memory type */ 175 if (spd.mem_type != SPD_MEMTYPE_DDR && spd.mem_type != SPD_MEMTYPE_DDR2) { 176 debug("DDR: Module mem type is %02X\n", spd.mem_type); 177 return 0; 178 } 179 180 /* Check the number of physical bank */ 181 if (spd.mem_type == SPD_MEMTYPE_DDR) { 182 n_ranks = spd.nrows; 183 } else { 184 n_ranks = (spd.nrows & 0x7) + 1; 185 } 186 187 if (n_ranks > 2) { 188 printf("DDR: The number of physical bank is %02X\n", n_ranks); 189 return 0; 190 } 191 192 /* Check if the number of row of the module is in the range of DDRC */ 193 if (spd.nrow_addr < 12 || spd.nrow_addr > 15) { 194 printf("DDR: Row number is out of range of DDRC, row=%02X\n", 195 spd.nrow_addr); 196 return 0; 197 } 198 199 /* Check if the number of col of the module is in the range of DDRC */ 200 if (spd.ncol_addr < 8 || spd.ncol_addr > 11) { 201 printf("DDR: Col number is out of range of DDRC, col=%02X\n", 202 spd.ncol_addr); 203 return 0; 204 } 205 206 #ifdef CONFIG_SYS_DDRCDR_VALUE 207 /* 208 * Adjust DDR II IO voltage biasing. It just makes it work. 209 */ 210 if(spd.mem_type == SPD_MEMTYPE_DDR2) { 211 immap->sysconf.ddrcdr = CONFIG_SYS_DDRCDR_VALUE; 212 } 213 udelay(50000); 214 #endif 215 216 /* 217 * ODT configuration recommendation from DDR Controller Chapter. 218 */ 219 odt_rd_cfg = 0; /* Never assert ODT */ 220 odt_wr_cfg = 0; /* Never assert ODT */ 221 if (spd.mem_type == SPD_MEMTYPE_DDR2) { 222 odt_wr_cfg = 1; /* Assert ODT on writes to CSn */ 223 } 224 225 /* Setup DDR chip select register */ 226 #ifdef CONFIG_SYS_83XX_DDR_USES_CS0 227 ddr->csbnds[0].csbnds = (banksize(spd.row_dens) >> 24) - 1; 228 ddr->cs_config[0] = ( 1 << 31 229 | (odt_rd_cfg << 20) 230 | (odt_wr_cfg << 16) 231 | ((spd.nbanks == 8 ? 1 : 0) << 14) 232 | ((spd.nrow_addr - 12) << 8) 233 | (spd.ncol_addr - 8) ); 234 debug("\n"); 235 debug("cs0_bnds = 0x%08x\n",ddr->csbnds[0].csbnds); 236 debug("cs0_config = 0x%08x\n",ddr->cs_config[0]); 237 238 if (n_ranks == 2) { 239 ddr->csbnds[1].csbnds = ( (banksize(spd.row_dens) >> 8) 240 | ((banksize(spd.row_dens) >> 23) - 1) ); 241 ddr->cs_config[1] = ( 1<<31 242 | (odt_rd_cfg << 20) 243 | (odt_wr_cfg << 16) 244 | ((spd.nbanks == 8 ? 1 : 0) << 14) 245 | ((spd.nrow_addr - 12) << 8) 246 | (spd.ncol_addr - 8) ); 247 debug("cs1_bnds = 0x%08x\n",ddr->csbnds[1].csbnds); 248 debug("cs1_config = 0x%08x\n",ddr->cs_config[1]); 249 } 250 251 #else 252 ddr->csbnds[2].csbnds = (banksize(spd.row_dens) >> 24) - 1; 253 ddr->cs_config[2] = ( 1 << 31 254 | (odt_rd_cfg << 20) 255 | (odt_wr_cfg << 16) 256 | ((spd.nbanks == 8 ? 1 : 0) << 14) 257 | ((spd.nrow_addr - 12) << 8) 258 | (spd.ncol_addr - 8) ); 259 debug("\n"); 260 debug("cs2_bnds = 0x%08x\n",ddr->csbnds[2].csbnds); 261 debug("cs2_config = 0x%08x\n",ddr->cs_config[2]); 262 263 if (n_ranks == 2) { 264 ddr->csbnds[3].csbnds = ( (banksize(spd.row_dens) >> 8) 265 | ((banksize(spd.row_dens) >> 23) - 1) ); 266 ddr->cs_config[3] = ( 1<<31 267 | (odt_rd_cfg << 20) 268 | (odt_wr_cfg << 16) 269 | ((spd.nbanks == 8 ? 1 : 0) << 14) 270 | ((spd.nrow_addr - 12) << 8) 271 | (spd.ncol_addr - 8) ); 272 debug("cs3_bnds = 0x%08x\n",ddr->csbnds[3].csbnds); 273 debug("cs3_config = 0x%08x\n",ddr->cs_config[3]); 274 } 275 #endif 276 277 /* 278 * Figure out memory size in Megabytes. 279 */ 280 memsize = n_ranks * banksize(spd.row_dens) / 0x100000; 281 282 /* 283 * First supported LAW size is 16M, at LAWAR_SIZE_16M == 23. 284 */ 285 law_size = 19 + __ilog2(memsize); 286 287 /* 288 * Set up LAWBAR for all of DDR. 289 */ 290 ecm->bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000; 291 ecm->ar = (LAWAR_EN | LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & law_size)); 292 debug("DDR:bar=0x%08x\n", ecm->bar); 293 debug("DDR:ar=0x%08x\n", ecm->ar); 294 295 /* 296 * Find the largest CAS by locating the highest 1 bit 297 * in the spd.cas_lat field. Translate it to a DDR 298 * controller field value: 299 * 300 * CAS Lat DDR I DDR II Ctrl 301 * Clocks SPD Bit SPD Bit Value 302 * ------- ------- ------- ----- 303 * 1.0 0 0001 304 * 1.5 1 0010 305 * 2.0 2 2 0011 306 * 2.5 3 0100 307 * 3.0 4 3 0101 308 * 3.5 5 0110 309 * 4.0 6 4 0111 310 * 4.5 1000 311 * 5.0 5 1001 312 */ 313 caslat = __ilog2(spd.cas_lat); 314 if ((spd.mem_type == SPD_MEMTYPE_DDR) 315 && (caslat > 6)) { 316 printf("DDR I: Invalid SPD CAS Latency: 0x%x.\n", spd.cas_lat); 317 return 0; 318 } else if (spd.mem_type == SPD_MEMTYPE_DDR2 319 && (caslat < 2 || caslat > 5)) { 320 printf("DDR II: Invalid SPD CAS Latency: 0x%x.\n", 321 spd.cas_lat); 322 return 0; 323 } 324 debug("DDR: caslat SPD bit is %d\n", caslat); 325 326 max_bus_clk = 1000 *10 / (((spd.clk_cycle & 0xF0) >> 4) * 10 327 + (spd.clk_cycle & 0x0f)); 328 max_data_rate = max_bus_clk * 2; 329 330 debug("DDR:Module maximum data rate is: %d MHz\n", max_data_rate); 331 332 ddrc_clk = gd->mem_clk / 1000000; 333 effective_data_rate = 0; 334 335 if (max_data_rate >= 460) { /* it is DDR2-800, 667, 533 */ 336 if (spd.cas_lat & 0x08) 337 caslat = 3; 338 else 339 caslat = 4; 340 if (ddrc_clk <= 460 && ddrc_clk > 350) 341 effective_data_rate = 400; 342 else if (ddrc_clk <=350 && ddrc_clk > 280) 343 effective_data_rate = 333; 344 else if (ddrc_clk <= 280 && ddrc_clk > 230) 345 effective_data_rate = 266; 346 else 347 effective_data_rate = 200; 348 } else if (max_data_rate >= 390 && max_data_rate < 460) { /* it is DDR 400 */ 349 if (ddrc_clk <= 460 && ddrc_clk > 350) { 350 /* DDR controller clk at 350~460 */ 351 effective_data_rate = 400; /* 5ns */ 352 caslat = caslat; 353 } else if (ddrc_clk <= 350 && ddrc_clk > 280) { 354 /* DDR controller clk at 280~350 */ 355 effective_data_rate = 333; /* 6ns */ 356 if (spd.clk_cycle2 == 0x60) 357 caslat = caslat - 1; 358 else 359 caslat = caslat; 360 } else if (ddrc_clk <= 280 && ddrc_clk > 230) { 361 /* DDR controller clk at 230~280 */ 362 effective_data_rate = 266; /* 7.5ns */ 363 if (spd.clk_cycle3 == 0x75) 364 caslat = caslat - 2; 365 else if (spd.clk_cycle2 == 0x75) 366 caslat = caslat - 1; 367 else 368 caslat = caslat; 369 } else if (ddrc_clk <= 230 && ddrc_clk > 90) { 370 /* DDR controller clk at 90~230 */ 371 effective_data_rate = 200; /* 10ns */ 372 if (spd.clk_cycle3 == 0xa0) 373 caslat = caslat - 2; 374 else if (spd.clk_cycle2 == 0xa0) 375 caslat = caslat - 1; 376 else 377 caslat = caslat; 378 } 379 } else if (max_data_rate >= 323) { /* it is DDR 333 */ 380 if (ddrc_clk <= 350 && ddrc_clk > 280) { 381 /* DDR controller clk at 280~350 */ 382 effective_data_rate = 333; /* 6ns */ 383 caslat = caslat; 384 } else if (ddrc_clk <= 280 && ddrc_clk > 230) { 385 /* DDR controller clk at 230~280 */ 386 effective_data_rate = 266; /* 7.5ns */ 387 if (spd.clk_cycle2 == 0x75) 388 caslat = caslat - 1; 389 else 390 caslat = caslat; 391 } else if (ddrc_clk <= 230 && ddrc_clk > 90) { 392 /* DDR controller clk at 90~230 */ 393 effective_data_rate = 200; /* 10ns */ 394 if (spd.clk_cycle3 == 0xa0) 395 caslat = caslat - 2; 396 else if (spd.clk_cycle2 == 0xa0) 397 caslat = caslat - 1; 398 else 399 caslat = caslat; 400 } 401 } else if (max_data_rate >= 256) { /* it is DDR 266 */ 402 if (ddrc_clk <= 350 && ddrc_clk > 280) { 403 /* DDR controller clk at 280~350 */ 404 printf("DDR: DDR controller freq is more than " 405 "max data rate of the module\n"); 406 return 0; 407 } else if (ddrc_clk <= 280 && ddrc_clk > 230) { 408 /* DDR controller clk at 230~280 */ 409 effective_data_rate = 266; /* 7.5ns */ 410 caslat = caslat; 411 } else if (ddrc_clk <= 230 && ddrc_clk > 90) { 412 /* DDR controller clk at 90~230 */ 413 effective_data_rate = 200; /* 10ns */ 414 if (spd.clk_cycle2 == 0xa0) 415 caslat = caslat - 1; 416 } 417 } else if (max_data_rate >= 190) { /* it is DDR 200 */ 418 if (ddrc_clk <= 350 && ddrc_clk > 230) { 419 /* DDR controller clk at 230~350 */ 420 printf("DDR: DDR controller freq is more than " 421 "max data rate of the module\n"); 422 return 0; 423 } else if (ddrc_clk <= 230 && ddrc_clk > 90) { 424 /* DDR controller clk at 90~230 */ 425 effective_data_rate = 200; /* 10ns */ 426 caslat = caslat; 427 } 428 } 429 430 debug("DDR:Effective data rate is: %dMHz\n", effective_data_rate); 431 debug("DDR:The MSB 1 of CAS Latency is: %d\n", caslat); 432 433 /* 434 * Errata DDR6 work around: input enable 2 cycles earlier. 435 * including MPC834x Rev1.0/1.1 and MPC8360 Rev1.1/1.2. 436 */ 437 if(PVR_MAJ(pvr) <= 1 && spd.mem_type == SPD_MEMTYPE_DDR){ 438 if (caslat == 2) 439 ddr->debug_reg = 0x201c0000; /* CL=2 */ 440 else if (caslat == 3) 441 ddr->debug_reg = 0x202c0000; /* CL=2.5 */ 442 else if (caslat == 4) 443 ddr->debug_reg = 0x202c0000; /* CL=3.0 */ 444 445 __asm__ __volatile__ ("sync"); 446 447 debug("Errata DDR6 (debug_reg=0x%08x)\n", ddr->debug_reg); 448 } 449 450 /* 451 * Convert caslat clocks to DDR controller value. 452 * Force caslat_ctrl to be DDR Controller field-sized. 453 */ 454 if (spd.mem_type == SPD_MEMTYPE_DDR) { 455 caslat_ctrl = (caslat + 1) & 0x07; 456 } else { 457 caslat_ctrl = (2 * caslat - 1) & 0x0f; 458 } 459 460 debug("DDR: effective data rate is %d MHz\n", effective_data_rate); 461 debug("DDR: caslat SPD bit is %d, controller field is 0x%x\n", 462 caslat, caslat_ctrl); 463 464 /* 465 * Timing Config 0. 466 * Avoid writing for DDR I. 467 */ 468 if (spd.mem_type == SPD_MEMTYPE_DDR2) { 469 unsigned char taxpd_clk = 8; /* By the book. */ 470 unsigned char tmrd_clk = 2; /* By the book. */ 471 unsigned char act_pd_exit = 2; /* Empirical? */ 472 unsigned char pre_pd_exit = 6; /* Empirical? */ 473 474 ddr->timing_cfg_0 = (0 475 | ((act_pd_exit & 0x7) << 20) /* ACT_PD_EXIT */ 476 | ((pre_pd_exit & 0x7) << 16) /* PRE_PD_EXIT */ 477 | ((taxpd_clk & 0xf) << 8) /* ODT_PD_EXIT */ 478 | ((tmrd_clk & 0xf) << 0) /* MRS_CYC */ 479 ); 480 debug("DDR: timing_cfg_0 = 0x%08x\n", ddr->timing_cfg_0); 481 } 482 483 /* 484 * For DDR I, WRREC(Twr) and WRTORD(Twtr) are not in SPD, 485 * use conservative value. 486 * For DDR II, they are bytes 36 and 37, in quarter nanos. 487 */ 488 489 if (spd.mem_type == SPD_MEMTYPE_DDR) { 490 twr_clk = 3; /* Clocks */ 491 twtr_clk = 1; /* Clocks */ 492 } else { 493 twr_clk = picos_to_clk(spd.twr * 250); 494 twtr_clk = picos_to_clk(spd.twtr * 250); 495 if (twtr_clk < 2) 496 twtr_clk = 2; 497 } 498 499 /* 500 * Calculate Trfc, in picos. 501 * DDR I: Byte 42 straight up in ns. 502 * DDR II: Byte 40 and 42 swizzled some, in ns. 503 */ 504 if (spd.mem_type == SPD_MEMTYPE_DDR) { 505 trfc = spd.trfc * 1000; /* up to ps */ 506 } else { 507 unsigned int byte40_table_ps[8] = { 508 0, 509 250, 510 330, 511 500, 512 660, 513 750, 514 0, 515 0 516 }; 517 518 trfc = (((spd.trctrfc_ext & 0x1) * 256) + spd.trfc) * 1000 519 + byte40_table_ps[(spd.trctrfc_ext >> 1) & 0x7]; 520 } 521 trfc_clk = picos_to_clk(trfc); 522 523 /* 524 * Trcd, Byte 29, from quarter nanos to ps and clocks. 525 */ 526 trcd_clk = picos_to_clk(spd.trcd * 250) & 0x7; 527 528 /* 529 * Convert trfc_clk to DDR controller fields. DDR I should 530 * fit in the REFREC field (16-19) of TIMING_CFG_1, but the 531 * 83xx controller has an extended REFREC field of three bits. 532 * The controller automatically adds 8 clocks to this value, 533 * so preadjust it down 8 first before splitting it up. 534 */ 535 trfc_low = (trfc_clk - 8) & 0xf; 536 trfc_high = ((trfc_clk - 8) >> 4) & 0x3; 537 538 ddr->timing_cfg_1 = 539 (((picos_to_clk(spd.trp * 250) & 0x07) << 28 ) | /* PRETOACT */ 540 ((picos_to_clk(spd.tras * 1000) & 0x0f ) << 24 ) | /* ACTTOPRE */ 541 (trcd_clk << 20 ) | /* ACTTORW */ 542 (caslat_ctrl << 16 ) | /* CASLAT */ 543 (trfc_low << 12 ) | /* REFEC */ 544 ((twr_clk & 0x07) << 8) | /* WRRREC */ 545 ((picos_to_clk(spd.trrd * 250) & 0x07) << 4) | /* ACTTOACT */ 546 ((twtr_clk & 0x07) << 0) /* WRTORD */ 547 ); 548 549 /* 550 * Additive Latency 551 * For DDR I, 0. 552 * For DDR II, with ODT enabled, use "a value" less than ACTTORW, 553 * which comes from Trcd, and also note that: 554 * add_lat + caslat must be >= 4 555 */ 556 add_lat = 0; 557 if (spd.mem_type == SPD_MEMTYPE_DDR2 558 && (odt_wr_cfg || odt_rd_cfg) 559 && (caslat < 4)) { 560 add_lat = 4 - caslat; 561 if ((add_lat + caslat) < 4) { 562 add_lat = 0; 563 } 564 } 565 566 /* 567 * Write Data Delay 568 * Historically 0x2 == 4/8 clock delay. 569 * Empirically, 0x3 == 6/8 clock delay is suggested for DDR I 266. 570 */ 571 wr_data_delay = 2; 572 #ifdef CONFIG_SYS_DDR_WRITE_DATA_DELAY 573 wr_data_delay = CONFIG_SYS_DDR_WRITE_DATA_DELAY; 574 #endif 575 576 /* 577 * Write Latency 578 * Read to Precharge 579 * Minimum CKE Pulse Width. 580 * Four Activate Window 581 */ 582 if (spd.mem_type == SPD_MEMTYPE_DDR) { 583 /* 584 * This is a lie. It should really be 1, but if it is 585 * set to 1, bits overlap into the old controller's 586 * otherwise unused ACSM field. If we leave it 0, then 587 * the HW will magically treat it as 1 for DDR 1. Oh Yea. 588 */ 589 wr_lat = 0; 590 591 trtp_clk = 2; /* By the book. */ 592 cke_min_clk = 1; /* By the book. */ 593 four_act = 1; /* By the book. */ 594 595 } else { 596 wr_lat = caslat - 1; 597 598 /* Convert SPD value from quarter nanos to picos. */ 599 trtp_clk = picos_to_clk(spd.trtp * 250); 600 if (trtp_clk < 2) 601 trtp_clk = 2; 602 trtp_clk += add_lat; 603 604 cke_min_clk = 3; /* By the book. */ 605 four_act = picos_to_clk(37500); /* By the book. 1k pages? */ 606 } 607 608 /* 609 * Empirically set ~MCAS-to-preamble override for DDR 2. 610 * Your milage will vary. 611 */ 612 cpo = 0; 613 if (spd.mem_type == SPD_MEMTYPE_DDR2) { 614 #ifdef CONFIG_SYS_DDR_CPO 615 cpo = CONFIG_SYS_DDR_CPO; 616 #else 617 if (effective_data_rate == 266) { 618 cpo = 0x4; /* READ_LAT + 1/2 */ 619 } else if (effective_data_rate == 333) { 620 cpo = 0x6; /* READ_LAT + 1 */ 621 } else if (effective_data_rate == 400) { 622 cpo = 0x7; /* READ_LAT + 5/4 */ 623 } else { 624 /* Automatic calibration */ 625 cpo = 0x1f; 626 } 627 #endif 628 } 629 630 ddr->timing_cfg_2 = (0 631 | ((add_lat & 0x7) << 28) /* ADD_LAT */ 632 | ((cpo & 0x1f) << 23) /* CPO */ 633 | ((wr_lat & 0x7) << 19) /* WR_LAT */ 634 | ((trtp_clk & 0x7) << 13) /* RD_TO_PRE */ 635 | ((wr_data_delay & 0x7) << 10) /* WR_DATA_DELAY */ 636 | ((cke_min_clk & 0x7) << 6) /* CKE_PLS */ 637 | ((four_act & 0x1f) << 0) /* FOUR_ACT */ 638 ); 639 640 debug("DDR:timing_cfg_1=0x%08x\n", ddr->timing_cfg_1); 641 debug("DDR:timing_cfg_2=0x%08x\n", ddr->timing_cfg_2); 642 643 /* Check DIMM data bus width */ 644 if (spd.dataw_lsb < 64) { 645 if (spd.mem_type == SPD_MEMTYPE_DDR) 646 burstlen = 0x03; /* 32 bit data bus, burst len is 8 */ 647 else 648 burstlen = 0x02; /* 32 bit data bus, burst len is 4 */ 649 debug("\n DDR DIMM: data bus width is 32 bit"); 650 } else { 651 burstlen = 0x02; /* Others act as 64 bit bus, burst len is 4 */ 652 debug("\n DDR DIMM: data bus width is 64 bit"); 653 } 654 655 /* Is this an ECC DDR chip? */ 656 if (spd.config == 0x02) 657 debug(" with ECC\n"); 658 else 659 debug(" without ECC\n"); 660 661 /* Burst length is always 4 for 64 bit data bus, 8 for 32 bit data bus, 662 Burst type is sequential 663 */ 664 if (spd.mem_type == SPD_MEMTYPE_DDR) { 665 switch (caslat) { 666 case 1: 667 ddr->sdram_mode = 0x50 | burstlen; /* CL=1.5 */ 668 break; 669 case 2: 670 ddr->sdram_mode = 0x20 | burstlen; /* CL=2.0 */ 671 break; 672 case 3: 673 ddr->sdram_mode = 0x60 | burstlen; /* CL=2.5 */ 674 break; 675 case 4: 676 ddr->sdram_mode = 0x30 | burstlen; /* CL=3.0 */ 677 break; 678 default: 679 printf("DDR:only CL 1.5, 2.0, 2.5, 3.0 is supported\n"); 680 return 0; 681 } 682 } else { 683 mode_odt_enable = 0x0; /* Default disabled */ 684 if (odt_wr_cfg || odt_rd_cfg) { 685 /* 686 * Bits 6 and 2 in Extended MRS(1) 687 * Bit 2 == 0x04 == 75 Ohm, with 2 DIMM modules. 688 * Bit 6 == 0x40 == 150 Ohm, with 1 DIMM module. 689 */ 690 mode_odt_enable = 0x40; /* 150 Ohm */ 691 } 692 693 ddr->sdram_mode = 694 (0 695 | (1 << (16 + 10)) /* DQS Differential disable */ 696 #ifdef CONFIG_SYS_DDR_MODE_WEAK 697 | (1 << (16 + 1)) /* weak driver (~60%) */ 698 #endif 699 | (add_lat << (16 + 3)) /* Additive Latency in EMRS1 */ 700 | (mode_odt_enable << 16) /* ODT Enable in EMRS1 */ 701 | ((twr_clk - 1) << 9) /* Write Recovery Autopre */ 702 | (caslat << 4) /* caslat */ 703 | (burstlen << 0) /* Burst length */ 704 ); 705 } 706 debug("DDR:sdram_mode=0x%08x\n", ddr->sdram_mode); 707 708 /* 709 * Clear EMRS2 and EMRS3. 710 */ 711 ddr->sdram_mode2 = 0; 712 debug("DDR: sdram_mode2 = 0x%08x\n", ddr->sdram_mode2); 713 714 switch (spd.refresh) { 715 case 0x00: 716 case 0x80: 717 refresh_clk = picos_to_clk(15625000); 718 break; 719 case 0x01: 720 case 0x81: 721 refresh_clk = picos_to_clk(3900000); 722 break; 723 case 0x02: 724 case 0x82: 725 refresh_clk = picos_to_clk(7800000); 726 break; 727 case 0x03: 728 case 0x83: 729 refresh_clk = picos_to_clk(31300000); 730 break; 731 case 0x04: 732 case 0x84: 733 refresh_clk = picos_to_clk(62500000); 734 break; 735 case 0x05: 736 case 0x85: 737 refresh_clk = picos_to_clk(125000000); 738 break; 739 default: 740 refresh_clk = 0x512; 741 break; 742 } 743 744 /* 745 * Set BSTOPRE to 0x100 for page mode 746 * If auto-charge is used, set BSTOPRE = 0 747 */ 748 ddr->sdram_interval = ((refresh_clk & 0x3fff) << 16) | 0x100; 749 debug("DDR:sdram_interval=0x%08x\n", ddr->sdram_interval); 750 751 /* 752 * SDRAM Cfg 2 753 */ 754 odt_cfg = 0; 755 #ifndef CONFIG_NEVER_ASSERT_ODT_TO_CPU 756 if (odt_rd_cfg | odt_wr_cfg) { 757 odt_cfg = 0x2; /* ODT to IOs during reads */ 758 } 759 #endif 760 if (spd.mem_type == SPD_MEMTYPE_DDR2) { 761 ddr->sdram_cfg2 = (0 762 | (0 << 26) /* True DQS */ 763 | (odt_cfg << 21) /* ODT only read */ 764 | (1 << 12) /* 1 refresh at a time */ 765 ); 766 767 debug("DDR: sdram_cfg2 = 0x%08x\n", ddr->sdram_cfg2); 768 } 769 770 #ifdef CONFIG_SYS_DDR_SDRAM_CLK_CNTL /* Optional platform specific value */ 771 ddr->sdram_clk_cntl = CONFIG_SYS_DDR_SDRAM_CLK_CNTL; 772 #endif 773 debug("DDR:sdram_clk_cntl=0x%08x\n", ddr->sdram_clk_cntl); 774 775 asm("sync;isync"); 776 777 udelay(600); 778 779 /* 780 * Figure out the settings for the sdram_cfg register. Build up 781 * the value in 'sdram_cfg' before writing since the write into 782 * the register will actually enable the memory controller, and all 783 * settings must be done before enabling. 784 * 785 * sdram_cfg[0] = 1 (ddr sdram logic enable) 786 * sdram_cfg[1] = 1 (self-refresh-enable) 787 * sdram_cfg[5:7] = (SDRAM type = DDR SDRAM) 788 * 010 DDR 1 SDRAM 789 * 011 DDR 2 SDRAM 790 * sdram_cfg[12] = 0 (32_BE =0 , 64 bit bus mode) 791 * sdram_cfg[13] = 0 (8_BE =0, 4-beat bursts) 792 */ 793 if (spd.mem_type == SPD_MEMTYPE_DDR) 794 sdram_type = SDRAM_CFG_SDRAM_TYPE_DDR1; 795 else 796 sdram_type = SDRAM_CFG_SDRAM_TYPE_DDR2; 797 798 sdram_cfg = (0 799 | SDRAM_CFG_MEM_EN /* DDR enable */ 800 | SDRAM_CFG_SREN /* Self refresh */ 801 | sdram_type /* SDRAM type */ 802 ); 803 804 /* sdram_cfg[3] = RD_EN - registered DIMM enable */ 805 if (spd.mod_attr & 0x02) 806 sdram_cfg |= SDRAM_CFG_RD_EN; 807 808 /* The DIMM is 32bit width */ 809 if (spd.dataw_lsb < 64) { 810 if (spd.mem_type == SPD_MEMTYPE_DDR) 811 sdram_cfg |= SDRAM_CFG_32_BE | SDRAM_CFG_8_BE; 812 if (spd.mem_type == SPD_MEMTYPE_DDR2) 813 sdram_cfg |= SDRAM_CFG_32_BE; 814 } 815 816 ddrc_ecc_enable = 0; 817 818 #if defined(CONFIG_DDR_ECC) 819 /* Enable ECC with sdram_cfg[2] */ 820 if (spd.config == 0x02) { 821 sdram_cfg |= 0x20000000; 822 ddrc_ecc_enable = 1; 823 /* disable error detection */ 824 ddr->err_disable = ~ECC_ERROR_ENABLE; 825 /* set single bit error threshold to maximum value, 826 * reset counter to zero */ 827 ddr->err_sbe = (255 << ECC_ERROR_MAN_SBET_SHIFT) | 828 (0 << ECC_ERROR_MAN_SBEC_SHIFT); 829 } 830 831 debug("DDR:err_disable=0x%08x\n", ddr->err_disable); 832 debug("DDR:err_sbe=0x%08x\n", ddr->err_sbe); 833 #endif 834 debug(" DDRC ECC mode: %s\n", ddrc_ecc_enable ? "ON":"OFF"); 835 836 #if defined(CONFIG_DDR_2T_TIMING) 837 /* 838 * Enable 2T timing by setting sdram_cfg[16]. 839 */ 840 sdram_cfg |= SDRAM_CFG_2T_EN; 841 #endif 842 /* Enable controller, and GO! */ 843 ddr->sdram_cfg = sdram_cfg; 844 asm("sync;isync"); 845 udelay(500); 846 847 debug("DDR:sdram_cfg=0x%08x\n", ddr->sdram_cfg); 848 return memsize; /*in MBytes*/ 849 } 850 #endif /* CONFIG_SPD_EEPROM */ 851 852 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) 853 /* 854 * Use timebase counter, get_timer() is not availabe 855 * at this point of initialization yet. 856 */ 857 static __inline__ unsigned long get_tbms (void) 858 { 859 unsigned long tbl; 860 unsigned long tbu1, tbu2; 861 unsigned long ms; 862 unsigned long long tmp; 863 864 ulong tbclk = get_tbclk(); 865 866 /* get the timebase ticks */ 867 do { 868 asm volatile ("mftbu %0":"=r" (tbu1):); 869 asm volatile ("mftb %0":"=r" (tbl):); 870 asm volatile ("mftbu %0":"=r" (tbu2):); 871 } while (tbu1 != tbu2); 872 873 /* convert ticks to ms */ 874 tmp = (unsigned long long)(tbu1); 875 tmp = (tmp << 32); 876 tmp += (unsigned long long)(tbl); 877 ms = tmp/(tbclk/1000); 878 879 return ms; 880 } 881 882 /* 883 * Initialize all of memory for ECC, then enable errors. 884 */ 885 void ddr_enable_ecc(unsigned int dram_size) 886 { 887 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; 888 volatile ddr83xx_t *ddr= &immap->ddr; 889 unsigned long t_start, t_end; 890 register u64 *p; 891 register uint size; 892 unsigned int pattern[2]; 893 894 icache_enable(); 895 t_start = get_tbms(); 896 pattern[0] = 0xdeadbeef; 897 pattern[1] = 0xdeadbeef; 898 899 #if defined(CONFIG_DDR_ECC_INIT_VIA_DMA) 900 dma_meminit(pattern[0], dram_size); 901 #else 902 debug("ddr init: CPU FP write method\n"); 903 size = dram_size; 904 for (p = 0; p < (u64*)(size); p++) { 905 ppcDWstore((u32*)p, pattern); 906 } 907 __asm__ __volatile__ ("sync"); 908 #endif 909 910 t_end = get_tbms(); 911 icache_disable(); 912 913 debug("\nREADY!!\n"); 914 debug("ddr init duration: %ld ms\n", t_end - t_start); 915 916 /* Clear All ECC Errors */ 917 if ((ddr->err_detect & ECC_ERROR_DETECT_MME) == ECC_ERROR_DETECT_MME) 918 ddr->err_detect |= ECC_ERROR_DETECT_MME; 919 if ((ddr->err_detect & ECC_ERROR_DETECT_MBE) == ECC_ERROR_DETECT_MBE) 920 ddr->err_detect |= ECC_ERROR_DETECT_MBE; 921 if ((ddr->err_detect & ECC_ERROR_DETECT_SBE) == ECC_ERROR_DETECT_SBE) 922 ddr->err_detect |= ECC_ERROR_DETECT_SBE; 923 if ((ddr->err_detect & ECC_ERROR_DETECT_MSE) == ECC_ERROR_DETECT_MSE) 924 ddr->err_detect |= ECC_ERROR_DETECT_MSE; 925 926 /* Disable ECC-Interrupts */ 927 ddr->err_int_en &= ECC_ERR_INT_DISABLE; 928 929 /* Enable errors for ECC */ 930 ddr->err_disable &= ECC_ERROR_ENABLE; 931 932 __asm__ __volatile__ ("sync"); 933 __asm__ __volatile__ ("isync"); 934 } 935 #endif /* CONFIG_DDR_ECC */ 936