1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Freescale SerDes initialization routine 4 * 5 * Copyright 2007,2011 Freescale Semiconductor, Inc. 6 * Copyright (C) 2008 MontaVista Software, Inc. 7 * 8 * Author: Li Yang <leoli@freescale.com> 9 */ 10 11 #ifndef CONFIG_MPC83XX_SERDES 12 13 #include <config.h> 14 #include <common.h> 15 #include <asm/io.h> 16 #include <asm/fsl_mpc83xx_serdes.h> 17 18 /* SerDes registers */ 19 #define FSL_SRDSCR0_OFFS 0x0 20 #define FSL_SRDSCR0_DPP_1V2 0x00008800 21 #define FSL_SRDSCR0_TXEQA_MASK 0x00007000 22 #define FSL_SRDSCR0_TXEQA_SATA 0x00001000 23 #define FSL_SRDSCR0_TXEQE_MASK 0x00000700 24 #define FSL_SRDSCR0_TXEQE_SATA 0x00000100 25 #define FSL_SRDSCR1_OFFS 0x4 26 #define FSL_SRDSCR1_PLLBW 0x00000040 27 #define FSL_SRDSCR2_OFFS 0x8 28 #define FSL_SRDSCR2_VDD_1V2 0x00800000 29 #define FSL_SRDSCR2_SEIC_MASK 0x00001c1c 30 #define FSL_SRDSCR2_SEIC_SATA 0x00001414 31 #define FSL_SRDSCR2_SEIC_PEX 0x00001010 32 #define FSL_SRDSCR2_SEIC_SGMII 0x00000101 33 #define FSL_SRDSCR3_OFFS 0xc 34 #define FSL_SRDSCR3_KFR_SATA 0x10100000 35 #define FSL_SRDSCR3_KPH_SATA 0x04040000 36 #define FSL_SRDSCR3_SDFM_SATA_PEX 0x01010000 37 #define FSL_SRDSCR3_SDTXL_SATA 0x00000505 38 #define FSL_SRDSCR4_OFFS 0x10 39 #define FSL_SRDSCR4_PROT_SATA 0x00000808 40 #define FSL_SRDSCR4_PROT_PEX 0x00000101 41 #define FSL_SRDSCR4_PROT_SGMII 0x00000505 42 #define FSL_SRDSCR4_PLANE_X2 0x01000000 43 #define FSL_SRDSRSTCTL_OFFS 0x20 44 #define FSL_SRDSRSTCTL_RST 0x80000000 45 #define FSL_SRDSRSTCTL_SATA_RESET 0xf 46 47 void fsl_setup_serdes(u32 offset, char proto, u32 rfcks, char vdd) 48 { 49 void *regs = (void *)CONFIG_SYS_IMMR + offset; 50 u32 tmp; 51 52 /* 1.0V corevdd */ 53 if (vdd) { 54 /* DPPE/DPPA = 0 */ 55 tmp = in_be32(regs + FSL_SRDSCR0_OFFS); 56 tmp &= ~FSL_SRDSCR0_DPP_1V2; 57 out_be32(regs + FSL_SRDSCR0_OFFS, tmp); 58 59 /* VDD = 0 */ 60 tmp = in_be32(regs + FSL_SRDSCR2_OFFS); 61 tmp &= ~FSL_SRDSCR2_VDD_1V2; 62 out_be32(regs + FSL_SRDSCR2_OFFS, tmp); 63 } 64 65 /* protocol specific configuration */ 66 switch (proto) { 67 case FSL_SERDES_PROTO_SATA: 68 /* Set and clear reset bits */ 69 tmp = in_be32(regs + FSL_SRDSRSTCTL_OFFS); 70 tmp |= FSL_SRDSRSTCTL_SATA_RESET; 71 out_be32(regs + FSL_SRDSRSTCTL_OFFS, tmp); 72 udelay(1000); 73 tmp &= ~FSL_SRDSRSTCTL_SATA_RESET; 74 out_be32(regs + FSL_SRDSRSTCTL_OFFS, tmp); 75 76 /* Configure SRDSCR0 */ 77 clrsetbits_be32(regs + FSL_SRDSCR0_OFFS, 78 FSL_SRDSCR0_TXEQA_MASK | FSL_SRDSCR0_TXEQE_MASK, 79 FSL_SRDSCR0_TXEQA_SATA | FSL_SRDSCR0_TXEQE_SATA); 80 81 /* Configure SRDSCR1 */ 82 tmp = in_be32(regs + FSL_SRDSCR1_OFFS); 83 tmp &= ~FSL_SRDSCR1_PLLBW; 84 out_be32(regs + FSL_SRDSCR1_OFFS, tmp); 85 86 /* Configure SRDSCR2 */ 87 tmp = in_be32(regs + FSL_SRDSCR2_OFFS); 88 tmp &= ~FSL_SRDSCR2_SEIC_MASK; 89 tmp |= FSL_SRDSCR2_SEIC_SATA; 90 out_be32(regs + FSL_SRDSCR2_OFFS, tmp); 91 92 /* Configure SRDSCR3 */ 93 tmp = FSL_SRDSCR3_KFR_SATA | FSL_SRDSCR3_KPH_SATA | 94 FSL_SRDSCR3_SDFM_SATA_PEX | 95 FSL_SRDSCR3_SDTXL_SATA; 96 out_be32(regs + FSL_SRDSCR3_OFFS, tmp); 97 98 /* Configure SRDSCR4 */ 99 tmp = rfcks | FSL_SRDSCR4_PROT_SATA; 100 out_be32(regs + FSL_SRDSCR4_OFFS, tmp); 101 break; 102 case FSL_SERDES_PROTO_PEX: 103 case FSL_SERDES_PROTO_PEX_X2: 104 /* Configure SRDSCR1 */ 105 tmp = in_be32(regs + FSL_SRDSCR1_OFFS); 106 tmp |= FSL_SRDSCR1_PLLBW; 107 out_be32(regs + FSL_SRDSCR1_OFFS, tmp); 108 109 /* Configure SRDSCR2 */ 110 tmp = in_be32(regs + FSL_SRDSCR2_OFFS); 111 tmp &= ~FSL_SRDSCR2_SEIC_MASK; 112 tmp |= FSL_SRDSCR2_SEIC_PEX; 113 out_be32(regs + FSL_SRDSCR2_OFFS, tmp); 114 115 /* Configure SRDSCR3 */ 116 tmp = FSL_SRDSCR3_SDFM_SATA_PEX; 117 out_be32(regs + FSL_SRDSCR3_OFFS, tmp); 118 119 /* Configure SRDSCR4 */ 120 tmp = rfcks | FSL_SRDSCR4_PROT_PEX; 121 if (proto == FSL_SERDES_PROTO_PEX_X2) 122 tmp |= FSL_SRDSCR4_PLANE_X2; 123 out_be32(regs + FSL_SRDSCR4_OFFS, tmp); 124 break; 125 case FSL_SERDES_PROTO_SGMII: 126 /* Configure SRDSCR1 */ 127 tmp = in_be32(regs + FSL_SRDSCR1_OFFS); 128 tmp &= ~FSL_SRDSCR1_PLLBW; 129 out_be32(regs + FSL_SRDSCR1_OFFS, tmp); 130 131 /* Configure SRDSCR2 */ 132 tmp = in_be32(regs + FSL_SRDSCR2_OFFS); 133 tmp &= ~FSL_SRDSCR2_SEIC_MASK; 134 tmp |= FSL_SRDSCR2_SEIC_SGMII; 135 out_be32(regs + FSL_SRDSCR2_OFFS, tmp); 136 137 /* Configure SRDSCR3 */ 138 out_be32(regs + FSL_SRDSCR3_OFFS, 0); 139 140 /* Configure SRDSCR4 */ 141 tmp = rfcks | FSL_SRDSCR4_PROT_SGMII; 142 out_be32(regs + FSL_SRDSCR4_OFFS, tmp); 143 break; 144 default: 145 return; 146 } 147 148 /* Do a software reset */ 149 tmp = in_be32(regs + FSL_SRDSRSTCTL_OFFS); 150 tmp |= FSL_SRDSRSTCTL_RST; 151 out_be32(regs + FSL_SRDSRSTCTL_OFFS, tmp); 152 } 153 154 #endif /* !CONFIG_MPC83XX_SERDES */ 155