1 /* 2 * Copyright (C) 2007-2009 Freescale Semiconductor, Inc. 3 * Copyright (C) 2008-2009 MontaVista Software, Inc. 4 * 5 * Authors: Tony Li <tony.li@freescale.com> 6 * Anton Vorontsov <avorontsov@ru.mvista.com> 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21 * MA 02111-1307 USA 22 */ 23 24 #include <common.h> 25 #include <pci.h> 26 #include <mpc83xx.h> 27 #include <asm/io.h> 28 29 DECLARE_GLOBAL_DATA_PTR; 30 31 #define PCIE_MAX_BUSES 2 32 33 static struct { 34 u32 base; 35 u32 size; 36 } mpc83xx_pcie_cfg_space[] = { 37 { 38 .base = CONFIG_SYS_PCIE1_CFG_BASE, 39 .size = CONFIG_SYS_PCIE1_CFG_SIZE, 40 }, 41 #if defined(CONFIG_SYS_PCIE2_CFG_BASE) && defined(CONFIG_SYS_PCIE2_CFG_SIZE) 42 { 43 .base = CONFIG_SYS_PCIE2_CFG_BASE, 44 .size = CONFIG_SYS_PCIE2_CFG_SIZE, 45 }, 46 #endif 47 }; 48 49 #ifdef CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES 50 51 static int mpc83xx_pcie_remap_cfg(struct pci_controller *hose, pci_dev_t dev) 52 { 53 int bus = PCI_BUS(dev) - hose->first_busno; 54 immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; 55 pex83xx_t *pex = &immr->pciexp[bus]; 56 struct pex_outbound_window *out_win = &pex->bridge.pex_outbound_win[0]; 57 u8 devfn = PCI_DEV(dev) << 3 | PCI_FUNC(dev); 58 u32 dev_base = bus << 24 | devfn << 16; 59 60 if (hose->indirect_type == INDIRECT_TYPE_NO_PCIE_LINK) 61 return -1; 62 /* 63 * Workaround for the HW bug: for Type 0 configure transactions the 64 * PCI-E controller does not check the device number bits and just 65 * assumes that the device number bits are 0. 66 */ 67 if (devfn & 0xf8) 68 return -1; 69 70 out_le32(&out_win->tarl, dev_base); 71 return 0; 72 } 73 74 #define cfg_read(val, addr, type, op) \ 75 do { *val = op((type)(addr)); } while (0) 76 #define cfg_write(val, addr, type, op) \ 77 do { op((type *)(addr), (val)); } while (0) 78 79 #define cfg_read_err(val) do { *val = -1; } while (0) 80 #define cfg_write_err(val) do { } while (0) 81 82 #define PCIE_OP(rw, size, type, op) \ 83 static int pcie_##rw##_config_##size(struct pci_controller *hose, \ 84 pci_dev_t dev, int offset, \ 85 type val) \ 86 { \ 87 int ret; \ 88 \ 89 ret = mpc83xx_pcie_remap_cfg(hose, dev); \ 90 if (ret) { \ 91 cfg_##rw##_err(val); \ 92 return ret; \ 93 } \ 94 cfg_##rw(val, (void *)hose->cfg_addr + offset, type, op); \ 95 return 0; \ 96 } 97 98 PCIE_OP(read, byte, u8 *, in_8) 99 PCIE_OP(read, word, u16 *, in_le16) 100 PCIE_OP(read, dword, u32 *, in_le32) 101 PCIE_OP(write, byte, u8, out_8) 102 PCIE_OP(write, word, u16, out_le16) 103 PCIE_OP(write, dword, u32, out_le32) 104 105 static void mpc83xx_pcie_register_hose(int bus, struct pci_region *reg, 106 u8 link) 107 { 108 extern void disable_addr_trans(void); /* start.S */ 109 static struct pci_controller pcie_hose[PCIE_MAX_BUSES]; 110 struct pci_controller *hose = &pcie_hose[bus]; 111 int i; 112 113 /* 114 * There are no spare BATs to remap all PCI-E windows for U-Boot, so 115 * disable translations. In general, this is not great solution, and 116 * that's why we don't register PCI-E hoses by default. 117 */ 118 disable_addr_trans(); 119 120 for (i = 0; i < 2; i++, reg++) { 121 if (reg->size == 0) 122 break; 123 124 hose->regions[i] = *reg; 125 hose->region_count++; 126 } 127 128 i = hose->region_count++; 129 hose->regions[i].bus_start = 0; 130 hose->regions[i].phys_start = 0; 131 hose->regions[i].size = gd->ram_size; 132 hose->regions[i].flags = PCI_REGION_MEM | PCI_REGION_SYS_MEMORY; 133 134 i = hose->region_count++; 135 hose->regions[i].bus_start = CONFIG_SYS_IMMR; 136 hose->regions[i].phys_start = CONFIG_SYS_IMMR; 137 hose->regions[i].size = 0x100000; 138 hose->regions[i].flags = PCI_REGION_MEM | PCI_REGION_SYS_MEMORY; 139 140 hose->first_busno = pci_last_busno() + 1; 141 hose->last_busno = 0xff; 142 143 hose->cfg_addr = (unsigned int *)mpc83xx_pcie_cfg_space[bus].base; 144 145 pci_set_ops(hose, 146 pcie_read_config_byte, 147 pcie_read_config_word, 148 pcie_read_config_dword, 149 pcie_write_config_byte, 150 pcie_write_config_word, 151 pcie_write_config_dword); 152 153 if (!link) 154 hose->indirect_type = INDIRECT_TYPE_NO_PCIE_LINK; 155 156 pci_register_hose(hose); 157 158 #ifdef CONFIG_PCI_SCAN_SHOW 159 printf("PCI: Bus Dev VenId DevId Class Int\n"); 160 #endif 161 /* 162 * Hose scan. 163 */ 164 hose->last_busno = pci_hose_scan(hose); 165 } 166 167 #else 168 169 static void mpc83xx_pcie_register_hose(int bus, struct pci_region *reg, 170 u8 link) {} 171 172 #endif /* CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES */ 173 174 static void mpc83xx_pcie_init_bus(int bus, struct pci_region *reg) 175 { 176 immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; 177 pex83xx_t *pex = &immr->pciexp[bus]; 178 struct pex_outbound_window *out_win; 179 struct pex_inbound_window *in_win; 180 void *hose_cfg_base; 181 unsigned int ram_sz; 182 unsigned int barl; 183 unsigned int tar; 184 u16 reg16; 185 int i; 186 187 /* Enable pex csb bridge inbound & outbound transactions */ 188 out_le32(&pex->bridge.pex_csb_ctrl, 189 in_le32(&pex->bridge.pex_csb_ctrl) | PEX_CSB_CTRL_OBPIOE | 190 PEX_CSB_CTRL_IBPIOE); 191 192 /* Enable bridge outbound */ 193 out_le32(&pex->bridge.pex_csb_obctrl, PEX_CSB_OBCTRL_PIOE | 194 PEX_CSB_OBCTRL_MEMWE | PEX_CSB_OBCTRL_IOWE | 195 PEX_CSB_OBCTRL_CFGWE); 196 197 out_win = &pex->bridge.pex_outbound_win[0]; 198 out_le32(&out_win->ar, PEX_OWAR_EN | PEX_OWAR_TYPE_CFG | 199 mpc83xx_pcie_cfg_space[bus].size); 200 out_le32(&out_win->bar, mpc83xx_pcie_cfg_space[bus].base); 201 out_le32(&out_win->tarl, 0); 202 out_le32(&out_win->tarh, 0); 203 204 for (i = 0; i < 2; i++, reg++) { 205 u32 ar; 206 207 if (reg->size == 0) 208 break; 209 210 out_win = &pex->bridge.pex_outbound_win[i + 1]; 211 out_le32(&out_win->bar, reg->phys_start); 212 out_le32(&out_win->tarl, reg->bus_start); 213 out_le32(&out_win->tarh, 0); 214 ar = PEX_OWAR_EN | (reg->size & PEX_OWAR_SIZE); 215 if (reg->flags & PCI_REGION_IO) 216 ar |= PEX_OWAR_TYPE_IO; 217 else 218 ar |= PEX_OWAR_TYPE_MEM; 219 out_le32(&out_win->ar, ar); 220 } 221 222 out_le32(&pex->bridge.pex_csb_ibctrl, PEX_CSB_IBCTRL_PIOE); 223 224 ram_sz = gd->ram_size; 225 barl = 0; 226 tar = 0; 227 i = 0; 228 while (ram_sz > 0) { 229 in_win = &pex->bridge.pex_inbound_win[i]; 230 out_le32(&in_win->barl, barl); 231 out_le32(&in_win->barh, 0x0); 232 out_le32(&in_win->tar, tar); 233 if (ram_sz >= 0x10000000) { 234 /* The maxium windows size is 256M */ 235 out_le32(&in_win->ar, PEX_IWAR_EN | PEX_IWAR_NSOV | 236 PEX_IWAR_TYPE_PF | 0x0FFFF000); 237 barl += 0x10000000; 238 tar += 0x10000000; 239 ram_sz -= 0x10000000; 240 } else { 241 /* The UM is not clear here. 242 * So, round up to even Mb boundary */ 243 244 ram_sz = ram_sz >> (20 + 245 ((ram_sz & 0xFFFFF) ? 1 : 0)); 246 if (!(ram_sz % 2)) 247 ram_sz -= 1; 248 out_le32(&in_win->ar, PEX_IWAR_EN | PEX_IWAR_NSOV | 249 PEX_IWAR_TYPE_PF | (ram_sz << 20) | 0xFF000); 250 ram_sz = 0; 251 } 252 i++; 253 } 254 255 in_win = &pex->bridge.pex_inbound_win[i]; 256 out_le32(&in_win->barl, CONFIG_SYS_IMMR); 257 out_le32(&in_win->barh, 0); 258 out_le32(&in_win->tar, CONFIG_SYS_IMMR); 259 out_le32(&in_win->ar, PEX_IWAR_EN | 260 PEX_IWAR_TYPE_NO_PF | PEX_IWAR_SIZE_1M); 261 262 /* Enable the host virtual INTX interrupts */ 263 out_le32(&pex->bridge.pex_int_axi_misc_enb, 264 in_le32(&pex->bridge.pex_int_axi_misc_enb) | 0x1E0); 265 266 /* Hose configure header is memory-mapped */ 267 hose_cfg_base = (void *)pex; 268 269 get_clocks(); 270 /* Configure the PCIE controller core clock ratio */ 271 out_le32(hose_cfg_base + PEX_GCLK_RATIO, 272 (((bus ? gd->pciexp2_clk : gd->pciexp1_clk) / 1000000) * 16) 273 / 333); 274 udelay(1000000); 275 276 /* Do Type 1 bridge configuration */ 277 out_8(hose_cfg_base + PCI_PRIMARY_BUS, 0); 278 out_8(hose_cfg_base + PCI_SECONDARY_BUS, 1); 279 out_8(hose_cfg_base + PCI_SUBORDINATE_BUS, 255); 280 281 /* 282 * Write to Command register 283 */ 284 reg16 = in_le16(hose_cfg_base + PCI_COMMAND); 285 reg16 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO | 286 PCI_COMMAND_SERR | PCI_COMMAND_PARITY; 287 out_le16(hose_cfg_base + PCI_COMMAND, reg16); 288 289 /* 290 * Clear non-reserved bits in status register. 291 */ 292 out_le16(hose_cfg_base + PCI_STATUS, 0xffff); 293 out_8(hose_cfg_base + PCI_LATENCY_TIMER, 0x80); 294 out_8(hose_cfg_base + PCI_CACHE_LINE_SIZE, 0x08); 295 296 printf("PCIE%d: ", bus); 297 298 reg16 = in_le16(hose_cfg_base + PCI_LTSSM); 299 if (reg16 >= PCI_LTSSM_L0) 300 printf("link\n"); 301 else 302 printf("No link\n"); 303 304 mpc83xx_pcie_register_hose(bus, reg, reg16 >= PCI_LTSSM_L0); 305 } 306 307 /* 308 * The caller must have already set SCCR, SERDES and the PCIE_LAW BARs 309 * must have been set to cover all of the requested regions. 310 */ 311 void mpc83xx_pcie_init(int num_buses, struct pci_region **reg) 312 { 313 int i; 314 315 /* 316 * Release PCI RST Output signal. 317 * Power on to RST high must be at least 100 ms as per PCI spec. 318 * On warm boots only 1 ms is required, but we play it safe. 319 */ 320 udelay(100000); 321 322 if (num_buses > ARRAY_SIZE(mpc83xx_pcie_cfg_space)) { 323 printf("Second PCIE host contoller not configured!\n"); 324 num_buses = ARRAY_SIZE(mpc83xx_pcie_cfg_space); 325 } 326 327 for (i = 0; i < num_buses; i++) 328 mpc83xx_pcie_init_bus(i, reg[i]); 329 } 330