xref: /openbmc/u-boot/arch/powerpc/cpu/mpc83xx/ecc.c (revision d29d17d7)
1a47a12beSStefan Roese /*
2*d29d17d7SYork Sun  * Copyright (C) 2007-2011 Freescale Semiconductor, Inc.
3a47a12beSStefan Roese  *
4a47a12beSStefan Roese  * Dave Liu <daveliu@freescale.com>
5a47a12beSStefan Roese  * based on the contribution of Marian Balakowicz <m8@semihalf.com>
6a47a12beSStefan Roese  *
7a47a12beSStefan Roese  * See file CREDITS for list of people who contributed to this
8a47a12beSStefan Roese  * project.
9a47a12beSStefan Roese  *
10a47a12beSStefan Roese  * This program is free software; you can redistribute it and/or
11a47a12beSStefan Roese  * modify it under the terms of the GNU General Public License as
12a47a12beSStefan Roese  * published by the Free Software Foundation; either version 2 of
13a47a12beSStefan Roese  * the License, or (at your option) any later version.
14a47a12beSStefan Roese  */
15a47a12beSStefan Roese 
16a47a12beSStefan Roese #include <common.h>
17a47a12beSStefan Roese #include <mpc83xx.h>
18a47a12beSStefan Roese #include <command.h>
19a47a12beSStefan Roese 
20a47a12beSStefan Roese #if defined(CONFIG_DDR_ECC) && defined(CONFIG_DDR_ECC_CMD)
21a47a12beSStefan Roese void ecc_print_status(void)
22a47a12beSStefan Roese {
23*d29d17d7SYork Sun 	immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
24*d29d17d7SYork Sun #ifdef CONFIG_FSL_DDR2
25*d29d17d7SYork Sun 	ccsr_ddr_t *ddr = &immap->ddr;
26*d29d17d7SYork Sun #else
27*d29d17d7SYork Sun 	ddr83xx_t *ddr = &immap->ddr;
28*d29d17d7SYork Sun #endif
29a47a12beSStefan Roese 
30a47a12beSStefan Roese 	printf("\nECC mode: %s\n\n",
31a47a12beSStefan Roese 	       (ddr->sdram_cfg & SDRAM_CFG_ECC_EN) ? "ON" : "OFF");
32a47a12beSStefan Roese 
33a47a12beSStefan Roese 	/* Interrupts */
34a47a12beSStefan Roese 	printf("Memory Error Interrupt Enable:\n");
35a47a12beSStefan Roese 	printf("  Multiple-Bit Error Interrupt Enable: %d\n",
36a47a12beSStefan Roese 	       (ddr->err_int_en & ECC_ERR_INT_EN_MBEE) ? 1 : 0);
37a47a12beSStefan Roese 	printf("  Single-Bit Error Interrupt Enable: %d\n",
38a47a12beSStefan Roese 	       (ddr->err_int_en & ECC_ERR_INT_EN_SBEE) ? 1 : 0);
39a47a12beSStefan Roese 	printf("  Memory Select Error Interrupt Enable: %d\n\n",
40a47a12beSStefan Roese 	       (ddr->err_int_en & ECC_ERR_INT_EN_MSEE) ? 1 : 0);
41a47a12beSStefan Roese 
42a47a12beSStefan Roese 	/* Error disable */
43a47a12beSStefan Roese 	printf("Memory Error Disable:\n");
44a47a12beSStefan Roese 	printf("  Multiple-Bit Error Disable: %d\n",
45a47a12beSStefan Roese 	       (ddr->err_disable & ECC_ERROR_DISABLE_MBED) ? 1 : 0);
46a47a12beSStefan Roese 	printf("  Sinle-Bit Error Disable: %d\n",
47a47a12beSStefan Roese 	       (ddr->err_disable & ECC_ERROR_DISABLE_SBED) ? 1 : 0);
48a47a12beSStefan Roese 	printf("  Memory Select Error Disable: %d\n\n",
49a47a12beSStefan Roese 	       (ddr->err_disable & ECC_ERROR_DISABLE_MSED) ? 1 : 0);
50a47a12beSStefan Roese 
51a47a12beSStefan Roese 	/* Error injection */
52a47a12beSStefan Roese 	printf("Memory Data Path Error Injection Mask High/Low: %08x %08x\n",
53a47a12beSStefan Roese 	       ddr->data_err_inject_hi, ddr->data_err_inject_lo);
54a47a12beSStefan Roese 
55a47a12beSStefan Roese 	printf("Memory Data Path Error Injection Mask ECC:\n");
56a47a12beSStefan Roese 	printf("  ECC Mirror Byte: %d\n",
57a47a12beSStefan Roese 	       (ddr->ecc_err_inject & ECC_ERR_INJECT_EMB) ? 1 : 0);
58a47a12beSStefan Roese 	printf("  ECC Injection Enable: %d\n",
59a47a12beSStefan Roese 	       (ddr->ecc_err_inject & ECC_ERR_INJECT_EIEN) ? 1 : 0);
60a47a12beSStefan Roese 	printf("  ECC Error Injection Mask: 0x%02x\n\n",
61a47a12beSStefan Roese 	       ddr->ecc_err_inject & ECC_ERR_INJECT_EEIM);
62a47a12beSStefan Roese 
63a47a12beSStefan Roese 	/* SBE counter/threshold */
64a47a12beSStefan Roese 	printf("Memory Single-Bit Error Management (0..255):\n");
65a47a12beSStefan Roese 	printf("  Single-Bit Error Threshold: %d\n",
66a47a12beSStefan Roese 	       (ddr->err_sbe & ECC_ERROR_MAN_SBET) >> ECC_ERROR_MAN_SBET_SHIFT);
67a47a12beSStefan Roese 	printf("  Single-Bit Error Counter: %d\n\n",
68a47a12beSStefan Roese 	       (ddr->err_sbe & ECC_ERROR_MAN_SBEC) >> ECC_ERROR_MAN_SBEC_SHIFT);
69a47a12beSStefan Roese 
70a47a12beSStefan Roese 	/* Error detect */
71a47a12beSStefan Roese 	printf("Memory Error Detect:\n");
72a47a12beSStefan Roese 	printf("  Multiple Memory Errors: %d\n",
73a47a12beSStefan Roese 	       (ddr->err_detect & ECC_ERROR_DETECT_MME) ? 1 : 0);
74a47a12beSStefan Roese 	printf("  Multiple-Bit Error: %d\n",
75a47a12beSStefan Roese 	       (ddr->err_detect & ECC_ERROR_DETECT_MBE) ? 1 : 0);
76a47a12beSStefan Roese 	printf("  Single-Bit Error: %d\n",
77a47a12beSStefan Roese 	       (ddr->err_detect & ECC_ERROR_DETECT_SBE) ? 1 : 0);
78a47a12beSStefan Roese 	printf("  Memory Select Error: %d\n\n",
79a47a12beSStefan Roese 	       (ddr->err_detect & ECC_ERROR_DETECT_MSE) ? 1 : 0);
80a47a12beSStefan Roese 
81a47a12beSStefan Roese 	/* Capture data */
82a47a12beSStefan Roese 	printf("Memory Error Address Capture: 0x%08x\n", ddr->capture_address);
83a47a12beSStefan Roese 	printf("Memory Data Path Read Capture High/Low: %08x %08x\n",
84a47a12beSStefan Roese 	       ddr->capture_data_hi, ddr->capture_data_lo);
85a47a12beSStefan Roese 	printf("Memory Data Path Read Capture ECC: 0x%02x\n\n",
86a47a12beSStefan Roese 	       ddr->capture_ecc & CAPTURE_ECC_ECE);
87a47a12beSStefan Roese 
88a47a12beSStefan Roese 	printf("Memory Error Attributes Capture:\n");
89a47a12beSStefan Roese 	printf(" Data Beat Number: %d\n",
90a47a12beSStefan Roese 	       (ddr->capture_attributes & ECC_CAPT_ATTR_BNUM) >>
91a47a12beSStefan Roese 	       ECC_CAPT_ATTR_BNUM_SHIFT);
92a47a12beSStefan Roese 	printf("  Transaction Size: %d\n",
93a47a12beSStefan Roese 	       (ddr->capture_attributes & ECC_CAPT_ATTR_TSIZ) >>
94a47a12beSStefan Roese 	       ECC_CAPT_ATTR_TSIZ_SHIFT);
95a47a12beSStefan Roese 	printf("  Transaction Source: %d\n",
96a47a12beSStefan Roese 	       (ddr->capture_attributes & ECC_CAPT_ATTR_TSRC) >>
97a47a12beSStefan Roese 	       ECC_CAPT_ATTR_TSRC_SHIFT);
98a47a12beSStefan Roese 	printf("  Transaction Type: %d\n",
99a47a12beSStefan Roese 	       (ddr->capture_attributes & ECC_CAPT_ATTR_TTYP) >>
100a47a12beSStefan Roese 	       ECC_CAPT_ATTR_TTYP_SHIFT);
101a47a12beSStefan Roese 	printf("  Error Information Valid: %d\n\n",
102a47a12beSStefan Roese 	       ddr->capture_attributes & ECC_CAPT_ATTR_VLD);
103a47a12beSStefan Roese }
104a47a12beSStefan Roese 
10554841ab5SWolfgang Denk int do_ecc(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
106a47a12beSStefan Roese {
107*d29d17d7SYork Sun 	immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
108*d29d17d7SYork Sun #ifdef CONFIG_FSL_DDR2
109*d29d17d7SYork Sun 	ccsr_ddr_t *ddr = &immap->ddr;
110*d29d17d7SYork Sun #else
111*d29d17d7SYork Sun 	ddr83xx_t *ddr = &immap->ddr;
112*d29d17d7SYork Sun #endif
113a47a12beSStefan Roese 	volatile u32 val;
114a47a12beSStefan Roese 	u64 *addr;
115a47a12beSStefan Roese 	u32 count;
116a47a12beSStefan Roese 	register u64 *i;
117a47a12beSStefan Roese 	u32 ret[2];
118a47a12beSStefan Roese 	u32 pattern[2];
119a47a12beSStefan Roese 	u32 writeback[2];
120a47a12beSStefan Roese 
121a47a12beSStefan Roese 	/* The pattern is written into memory to generate error */
122a47a12beSStefan Roese 	pattern[0] = 0xfedcba98UL;
123a47a12beSStefan Roese 	pattern[1] = 0x76543210UL;
124a47a12beSStefan Roese 
125a47a12beSStefan Roese 	/* After injecting error, re-initialize the memory with the value */
126a47a12beSStefan Roese 	writeback[0] = 0x01234567UL;
127a47a12beSStefan Roese 	writeback[1] = 0x89abcdefUL;
128a47a12beSStefan Roese 
12947e26b1bSWolfgang Denk 	if (argc > 4)
13047e26b1bSWolfgang Denk 		return cmd_usage(cmdtp);
131a47a12beSStefan Roese 
132a47a12beSStefan Roese 	if (argc == 2) {
133a47a12beSStefan Roese 		if (strcmp(argv[1], "status") == 0) {
134a47a12beSStefan Roese 			ecc_print_status();
135a47a12beSStefan Roese 			return 0;
136a47a12beSStefan Roese 		} else if (strcmp(argv[1], "captureclear") == 0) {
137a47a12beSStefan Roese 			ddr->capture_address = 0;
138a47a12beSStefan Roese 			ddr->capture_data_hi = 0;
139a47a12beSStefan Roese 			ddr->capture_data_lo = 0;
140a47a12beSStefan Roese 			ddr->capture_ecc = 0;
141a47a12beSStefan Roese 			ddr->capture_attributes = 0;
142a47a12beSStefan Roese 			return 0;
143a47a12beSStefan Roese 		}
144a47a12beSStefan Roese 	}
145a47a12beSStefan Roese 	if (argc == 3) {
146a47a12beSStefan Roese 		if (strcmp(argv[1], "sbecnt") == 0) {
147a47a12beSStefan Roese 			val = simple_strtoul(argv[2], NULL, 10);
148a47a12beSStefan Roese 			if (val > 255) {
149a47a12beSStefan Roese 				printf("Incorrect Counter value, "
150a47a12beSStefan Roese 				       "should be 0..255\n");
151a47a12beSStefan Roese 				return 1;
152a47a12beSStefan Roese 			}
153a47a12beSStefan Roese 
154a47a12beSStefan Roese 			val = (val << ECC_ERROR_MAN_SBEC_SHIFT);
155a47a12beSStefan Roese 			val |= (ddr->err_sbe & ECC_ERROR_MAN_SBET);
156a47a12beSStefan Roese 
157a47a12beSStefan Roese 			ddr->err_sbe = val;
158a47a12beSStefan Roese 			return 0;
159a47a12beSStefan Roese 		} else if (strcmp(argv[1], "sbethr") == 0) {
160a47a12beSStefan Roese 			val = simple_strtoul(argv[2], NULL, 10);
161a47a12beSStefan Roese 			if (val > 255) {
162a47a12beSStefan Roese 				printf("Incorrect Counter value, "
163a47a12beSStefan Roese 				       "should be 0..255\n");
164a47a12beSStefan Roese 				return 1;
165a47a12beSStefan Roese 			}
166a47a12beSStefan Roese 
167a47a12beSStefan Roese 			val = (val << ECC_ERROR_MAN_SBET_SHIFT);
168a47a12beSStefan Roese 			val |= (ddr->err_sbe & ECC_ERROR_MAN_SBEC);
169a47a12beSStefan Roese 
170a47a12beSStefan Roese 			ddr->err_sbe = val;
171a47a12beSStefan Roese 			return 0;
172a47a12beSStefan Roese 		} else if (strcmp(argv[1], "errdisable") == 0) {
173a47a12beSStefan Roese 			val = ddr->err_disable;
174a47a12beSStefan Roese 
175a47a12beSStefan Roese 			if (strcmp(argv[2], "+sbe") == 0) {
176a47a12beSStefan Roese 				val |= ECC_ERROR_DISABLE_SBED;
177a47a12beSStefan Roese 			} else if (strcmp(argv[2], "+mbe") == 0) {
178a47a12beSStefan Roese 				val |= ECC_ERROR_DISABLE_MBED;
179a47a12beSStefan Roese 			} else if (strcmp(argv[2], "+mse") == 0) {
180a47a12beSStefan Roese 				val |= ECC_ERROR_DISABLE_MSED;
181a47a12beSStefan Roese 			} else if (strcmp(argv[2], "+all") == 0) {
182a47a12beSStefan Roese 				val |= (ECC_ERROR_DISABLE_SBED |
183a47a12beSStefan Roese 					ECC_ERROR_DISABLE_MBED |
184a47a12beSStefan Roese 					ECC_ERROR_DISABLE_MSED);
185a47a12beSStefan Roese 			} else if (strcmp(argv[2], "-sbe") == 0) {
186a47a12beSStefan Roese 				val &= ~ECC_ERROR_DISABLE_SBED;
187a47a12beSStefan Roese 			} else if (strcmp(argv[2], "-mbe") == 0) {
188a47a12beSStefan Roese 				val &= ~ECC_ERROR_DISABLE_MBED;
189a47a12beSStefan Roese 			} else if (strcmp(argv[2], "-mse") == 0) {
190a47a12beSStefan Roese 				val &= ~ECC_ERROR_DISABLE_MSED;
191a47a12beSStefan Roese 			} else if (strcmp(argv[2], "-all") == 0) {
192a47a12beSStefan Roese 				val &= ~(ECC_ERROR_DISABLE_SBED |
193a47a12beSStefan Roese 					 ECC_ERROR_DISABLE_MBED |
194a47a12beSStefan Roese 					 ECC_ERROR_DISABLE_MSED);
195a47a12beSStefan Roese 			} else {
196a47a12beSStefan Roese 				printf("Incorrect err_disable field\n");
197a47a12beSStefan Roese 				return 1;
198a47a12beSStefan Roese 			}
199a47a12beSStefan Roese 
200a47a12beSStefan Roese 			ddr->err_disable = val;
201a47a12beSStefan Roese 			__asm__ __volatile__("sync");
202a47a12beSStefan Roese 			__asm__ __volatile__("isync");
203a47a12beSStefan Roese 			return 0;
204a47a12beSStefan Roese 		} else if (strcmp(argv[1], "errdetectclr") == 0) {
205a47a12beSStefan Roese 			val = ddr->err_detect;
206a47a12beSStefan Roese 
207a47a12beSStefan Roese 			if (strcmp(argv[2], "mme") == 0) {
208a47a12beSStefan Roese 				val |= ECC_ERROR_DETECT_MME;
209a47a12beSStefan Roese 			} else if (strcmp(argv[2], "sbe") == 0) {
210a47a12beSStefan Roese 				val |= ECC_ERROR_DETECT_SBE;
211a47a12beSStefan Roese 			} else if (strcmp(argv[2], "mbe") == 0) {
212a47a12beSStefan Roese 				val |= ECC_ERROR_DETECT_MBE;
213a47a12beSStefan Roese 			} else if (strcmp(argv[2], "mse") == 0) {
214a47a12beSStefan Roese 				val |= ECC_ERROR_DETECT_MSE;
215a47a12beSStefan Roese 			} else if (strcmp(argv[2], "all") == 0) {
216a47a12beSStefan Roese 				val |= (ECC_ERROR_DETECT_MME |
217a47a12beSStefan Roese 					ECC_ERROR_DETECT_MBE |
218a47a12beSStefan Roese 					ECC_ERROR_DETECT_SBE |
219a47a12beSStefan Roese 					ECC_ERROR_DETECT_MSE);
220a47a12beSStefan Roese 			} else {
221a47a12beSStefan Roese 				printf("Incorrect err_detect field\n");
222a47a12beSStefan Roese 				return 1;
223a47a12beSStefan Roese 			}
224a47a12beSStefan Roese 
225a47a12beSStefan Roese 			ddr->err_detect = val;
226a47a12beSStefan Roese 			return 0;
227a47a12beSStefan Roese 		} else if (strcmp(argv[1], "injectdatahi") == 0) {
228a47a12beSStefan Roese 			val = simple_strtoul(argv[2], NULL, 16);
229a47a12beSStefan Roese 
230a47a12beSStefan Roese 			ddr->data_err_inject_hi = val;
231a47a12beSStefan Roese 			return 0;
232a47a12beSStefan Roese 		} else if (strcmp(argv[1], "injectdatalo") == 0) {
233a47a12beSStefan Roese 			val = simple_strtoul(argv[2], NULL, 16);
234a47a12beSStefan Roese 
235a47a12beSStefan Roese 			ddr->data_err_inject_lo = val;
236a47a12beSStefan Roese 			return 0;
237a47a12beSStefan Roese 		} else if (strcmp(argv[1], "injectecc") == 0) {
238a47a12beSStefan Roese 			val = simple_strtoul(argv[2], NULL, 16);
239a47a12beSStefan Roese 			if (val > 0xff) {
240a47a12beSStefan Roese 				printf("Incorrect ECC inject mask, "
241a47a12beSStefan Roese 				       "should be 0x00..0xff\n");
242a47a12beSStefan Roese 				return 1;
243a47a12beSStefan Roese 			}
244a47a12beSStefan Roese 			val |= (ddr->ecc_err_inject & ~ECC_ERR_INJECT_EEIM);
245a47a12beSStefan Roese 
246a47a12beSStefan Roese 			ddr->ecc_err_inject = val;
247a47a12beSStefan Roese 			return 0;
248a47a12beSStefan Roese 		} else if (strcmp(argv[1], "inject") == 0) {
249a47a12beSStefan Roese 			val = ddr->ecc_err_inject;
250a47a12beSStefan Roese 
251a47a12beSStefan Roese 			if (strcmp(argv[2], "en") == 0)
252a47a12beSStefan Roese 				val |= ECC_ERR_INJECT_EIEN;
253a47a12beSStefan Roese 			else if (strcmp(argv[2], "dis") == 0)
254a47a12beSStefan Roese 				val &= ~ECC_ERR_INJECT_EIEN;
255a47a12beSStefan Roese 			else
256a47a12beSStefan Roese 				printf("Incorrect command\n");
257a47a12beSStefan Roese 
258a47a12beSStefan Roese 			ddr->ecc_err_inject = val;
259a47a12beSStefan Roese 			__asm__ __volatile__("sync");
260a47a12beSStefan Roese 			__asm__ __volatile__("isync");
261a47a12beSStefan Roese 			return 0;
262a47a12beSStefan Roese 		} else if (strcmp(argv[1], "mirror") == 0) {
263a47a12beSStefan Roese 			val = ddr->ecc_err_inject;
264a47a12beSStefan Roese 
265a47a12beSStefan Roese 			if (strcmp(argv[2], "en") == 0)
266a47a12beSStefan Roese 				val |= ECC_ERR_INJECT_EMB;
267a47a12beSStefan Roese 			else if (strcmp(argv[2], "dis") == 0)
268a47a12beSStefan Roese 				val &= ~ECC_ERR_INJECT_EMB;
269a47a12beSStefan Roese 			else
270a47a12beSStefan Roese 				printf("Incorrect command\n");
271a47a12beSStefan Roese 
272a47a12beSStefan Roese 			ddr->ecc_err_inject = val;
273a47a12beSStefan Roese 			return 0;
274a47a12beSStefan Roese 		}
275a47a12beSStefan Roese 	}
276a47a12beSStefan Roese 	if (argc == 4) {
277a47a12beSStefan Roese 		if (strcmp(argv[1], "testdw") == 0) {
278a47a12beSStefan Roese 			addr = (u64 *) simple_strtoul(argv[2], NULL, 16);
279a47a12beSStefan Roese 			count = simple_strtoul(argv[3], NULL, 16);
280a47a12beSStefan Roese 
281a47a12beSStefan Roese 			if ((u32) addr % 8) {
282a47a12beSStefan Roese 				printf("Address not alligned on "
283a47a12beSStefan Roese 				       "double word boundary\n");
284a47a12beSStefan Roese 				return 1;
285a47a12beSStefan Roese 			}
286a47a12beSStefan Roese 			disable_interrupts();
287a47a12beSStefan Roese 
288a47a12beSStefan Roese 			for (i = addr; i < addr + count; i++) {
289a47a12beSStefan Roese 
290a47a12beSStefan Roese 				/* enable injects */
291a47a12beSStefan Roese 				ddr->ecc_err_inject |= ECC_ERR_INJECT_EIEN;
292a47a12beSStefan Roese 				__asm__ __volatile__("sync");
293a47a12beSStefan Roese 				__asm__ __volatile__("isync");
294a47a12beSStefan Roese 
295a47a12beSStefan Roese 				/* write memory location injecting errors */
296a47a12beSStefan Roese 				ppcDWstore((u32 *) i, pattern);
297a47a12beSStefan Roese 				__asm__ __volatile__("sync");
298a47a12beSStefan Roese 
299a47a12beSStefan Roese 				/* disable injects */
300a47a12beSStefan Roese 				ddr->ecc_err_inject &= ~ECC_ERR_INJECT_EIEN;
301a47a12beSStefan Roese 				__asm__ __volatile__("sync");
302a47a12beSStefan Roese 				__asm__ __volatile__("isync");
303a47a12beSStefan Roese 
304a47a12beSStefan Roese 				/* read data, this generates ECC error */
305a47a12beSStefan Roese 				ppcDWload((u32 *) i, ret);
306a47a12beSStefan Roese 				__asm__ __volatile__("sync");
307a47a12beSStefan Roese 
308a47a12beSStefan Roese 				/* re-initialize memory, double word write the location again,
309a47a12beSStefan Roese 				 * generates new ECC code this time */
310a47a12beSStefan Roese 				ppcDWstore((u32 *) i, writeback);
311a47a12beSStefan Roese 				__asm__ __volatile__("sync");
312a47a12beSStefan Roese 			}
313a47a12beSStefan Roese 			enable_interrupts();
314a47a12beSStefan Roese 			return 0;
315a47a12beSStefan Roese 		}
316a47a12beSStefan Roese 		if (strcmp(argv[1], "testword") == 0) {
317a47a12beSStefan Roese 			addr = (u64 *) simple_strtoul(argv[2], NULL, 16);
318a47a12beSStefan Roese 			count = simple_strtoul(argv[3], NULL, 16);
319a47a12beSStefan Roese 
320a47a12beSStefan Roese 			if ((u32) addr % 8) {
321a47a12beSStefan Roese 				printf("Address not alligned on "
322a47a12beSStefan Roese 				       "double word boundary\n");
323a47a12beSStefan Roese 				return 1;
324a47a12beSStefan Roese 			}
325a47a12beSStefan Roese 			disable_interrupts();
326a47a12beSStefan Roese 
327a47a12beSStefan Roese 			for (i = addr; i < addr + count; i++) {
328a47a12beSStefan Roese 
329a47a12beSStefan Roese 				/* enable injects */
330a47a12beSStefan Roese 				ddr->ecc_err_inject |= ECC_ERR_INJECT_EIEN;
331a47a12beSStefan Roese 				__asm__ __volatile__("sync");
332a47a12beSStefan Roese 				__asm__ __volatile__("isync");
333a47a12beSStefan Roese 
334a47a12beSStefan Roese 				/* write memory location injecting errors */
335a47a12beSStefan Roese 				*(u32 *) i = 0xfedcba98UL;
336a47a12beSStefan Roese 				__asm__ __volatile__("sync");
337a47a12beSStefan Roese 
338a47a12beSStefan Roese 				/* sub double word write,
339a47a12beSStefan Roese 				 * bus will read-modify-write,
340a47a12beSStefan Roese 				 * generates ECC error */
341a47a12beSStefan Roese 				*((u32 *) i + 1) = 0x76543210UL;
342a47a12beSStefan Roese 				__asm__ __volatile__("sync");
343a47a12beSStefan Roese 
344a47a12beSStefan Roese 				/* disable injects */
345a47a12beSStefan Roese 				ddr->ecc_err_inject &= ~ECC_ERR_INJECT_EIEN;
346a47a12beSStefan Roese 				__asm__ __volatile__("sync");
347a47a12beSStefan Roese 				__asm__ __volatile__("isync");
348a47a12beSStefan Roese 
349a47a12beSStefan Roese 				/* re-initialize memory,
350a47a12beSStefan Roese 				 * double word write the location again,
351a47a12beSStefan Roese 				 * generates new ECC code this time */
352a47a12beSStefan Roese 				ppcDWstore((u32 *) i, writeback);
353a47a12beSStefan Roese 				__asm__ __volatile__("sync");
354a47a12beSStefan Roese 			}
355a47a12beSStefan Roese 			enable_interrupts();
356a47a12beSStefan Roese 			return 0;
357a47a12beSStefan Roese 		}
358a47a12beSStefan Roese 	}
35947e26b1bSWolfgang Denk 	return cmd_usage(cmdtp);
360a47a12beSStefan Roese }
361a47a12beSStefan Roese 
362a47a12beSStefan Roese U_BOOT_CMD(ecc, 4, 0, do_ecc,
363a47a12beSStefan Roese 	   "support for DDR ECC features",
364a47a12beSStefan Roese 	   "status              - print out status info\n"
365a47a12beSStefan Roese 	   "ecc captureclear        - clear capture regs data\n"
366a47a12beSStefan Roese 	   "ecc sbecnt <val>        - set Single-Bit Error counter\n"
367a47a12beSStefan Roese 	   "ecc sbethr <val>        - set Single-Bit Threshold\n"
368a47a12beSStefan Roese 	   "ecc errdisable <flag>   - clear/set disable Memory Error Disable, flag:\n"
369a47a12beSStefan Roese 	   "  [-|+]sbe - Single-Bit Error\n"
370a47a12beSStefan Roese 	   "  [-|+]mbe - Multiple-Bit Error\n"
371a47a12beSStefan Roese 	   "  [-|+]mse - Memory Select Error\n"
372a47a12beSStefan Roese 	   "  [-|+]all - all errors\n"
373a47a12beSStefan Roese 	   "ecc errdetectclr <flag> - clear Memory Error Detect, flag:\n"
374a47a12beSStefan Roese 	   "  mme - Multiple Memory Errors\n"
375a47a12beSStefan Roese 	   "  sbe - Single-Bit Error\n"
376a47a12beSStefan Roese 	   "  mbe - Multiple-Bit Error\n"
377a47a12beSStefan Roese 	   "  mse - Memory Select Error\n"
378a47a12beSStefan Roese 	   "  all - all errors\n"
379a47a12beSStefan Roese 	   "ecc injectdatahi <hi>  - set Memory Data Path Error Injection Mask High\n"
380a47a12beSStefan Roese 	   "ecc injectdatalo <lo>  - set Memory Data Path Error Injection Mask Low\n"
381a47a12beSStefan Roese 	   "ecc injectecc <ecc>    - set ECC Error Injection Mask\n"
382a47a12beSStefan Roese 	   "ecc inject <en|dis>    - enable/disable error injection\n"
383a47a12beSStefan Roese 	   "ecc mirror <en|dis>    - enable/disable mirror byte\n"
384a47a12beSStefan Roese 	   "ecc testdw <addr> <cnt>  - test mem region with double word access:\n"
385a47a12beSStefan Roese 	   "  - enables injects\n"
386a47a12beSStefan Roese 	   "  - writes pattern injecting errors with double word access\n"
387a47a12beSStefan Roese 	   "  - disables injects\n"
388a47a12beSStefan Roese 	   "  - reads pattern back with double word access, generates error\n"
389a47a12beSStefan Roese 	   "  - re-inits memory\n"
390a47a12beSStefan Roese 	   "ecc testword <addr> <cnt>  - test mem region with word access:\n"
391a47a12beSStefan Roese 	   "  - enables injects\n"
392a47a12beSStefan Roese 	   "  - writes pattern injecting errors with word access\n"
393a47a12beSStefan Roese 	   "  - writes pattern with word access, generates error\n"
394a47a12beSStefan Roese 	   "  - disables injects\n" "  - re-inits memory");
395a47a12beSStefan Roese #endif
396