1 /*
2  * Copyright (C) 2004-2009 Freescale Semiconductor, Inc.
3  *
4  * SPDX-License-Identifier:	GPL-2.0+
5  */
6 
7 #include <common.h>
8 #include <mpc83xx.h>
9 #include <ioports.h>
10 #include <asm/io.h>
11 #ifdef CONFIG_USB_EHCI_FSL
12 #include <usb/ehci-ci.h>
13 #endif
14 
15 DECLARE_GLOBAL_DATA_PTR;
16 
17 #ifdef CONFIG_QE
18 extern qe_iop_conf_t qe_iop_conf_tab[];
19 extern void qe_config_iopin(u8 port, u8 pin, int dir,
20 			 int open_drain, int assign);
21 extern void qe_init(uint qe_base);
22 extern void qe_reset(void);
23 
24 static void config_qe_ioports(void)
25 {
26 	u8	port, pin;
27 	int	dir, open_drain, assign;
28 	int	i;
29 
30 	for (i = 0; qe_iop_conf_tab[i].assign != QE_IOP_TAB_END; i++) {
31 		port		= qe_iop_conf_tab[i].port;
32 		pin		= qe_iop_conf_tab[i].pin;
33 		dir		= qe_iop_conf_tab[i].dir;
34 		open_drain	= qe_iop_conf_tab[i].open_drain;
35 		assign		= qe_iop_conf_tab[i].assign;
36 		qe_config_iopin(port, pin, dir, open_drain, assign);
37 	}
38 }
39 #endif
40 
41 /*
42  * Breathe some life into the CPU...
43  *
44  * Set up the memory map,
45  * initialize a bunch of registers,
46  * initialize the UPM's
47  */
48 void cpu_init_f (volatile immap_t * im)
49 {
50 	__be32 acr_mask =
51 #ifdef CONFIG_SYS_ACR_PIPE_DEP /* Arbiter pipeline depth */
52 		ACR_PIPE_DEP |
53 #endif
54 #ifdef CONFIG_SYS_ACR_RPTCNT /* Arbiter repeat count */
55 		ACR_RPTCNT |
56 #endif
57 #ifdef CONFIG_SYS_ACR_APARK	/* Arbiter address parking mode */
58 		ACR_APARK |
59 #endif
60 #ifdef CONFIG_SYS_ACR_PARKM	/* Arbiter parking master */
61 		ACR_PARKM |
62 #endif
63 		0;
64 	__be32 acr_val =
65 #ifdef CONFIG_SYS_ACR_PIPE_DEP /* Arbiter pipeline depth */
66 		(CONFIG_SYS_ACR_PIPE_DEP << ACR_PIPE_DEP_SHIFT) |
67 #endif
68 #ifdef CONFIG_SYS_ACR_RPTCNT /* Arbiter repeat count */
69 		(CONFIG_SYS_ACR_RPTCNT << ACR_RPTCNT_SHIFT) |
70 #endif
71 #ifdef CONFIG_SYS_ACR_APARK	/* Arbiter address parking mode */
72 		(CONFIG_SYS_ACR_APARK << ACR_APARK_SHIFT) |
73 #endif
74 #ifdef CONFIG_SYS_ACR_PARKM	/* Arbiter parking master */
75 		(CONFIG_SYS_ACR_PARKM << ACR_PARKM_SHIFT) |
76 #endif
77 		0;
78 	__be32 spcr_mask =
79 #ifdef CONFIG_SYS_SPCR_OPT /* Optimize transactions between CSB and other dev */
80 		SPCR_OPT |
81 #endif
82 #ifdef CONFIG_SYS_SPCR_TSECEP /* all eTSEC's Emergency priority */
83 		SPCR_TSECEP |
84 #endif
85 #ifdef CONFIG_SYS_SPCR_TSEC1EP /* TSEC1 Emergency priority */
86 		SPCR_TSEC1EP |
87 #endif
88 #ifdef CONFIG_SYS_SPCR_TSEC2EP /* TSEC2 Emergency priority */
89 		SPCR_TSEC2EP |
90 #endif
91 		0;
92 	__be32 spcr_val =
93 #ifdef CONFIG_SYS_SPCR_OPT
94 		(CONFIG_SYS_SPCR_OPT << SPCR_OPT_SHIFT) |
95 #endif
96 #ifdef CONFIG_SYS_SPCR_TSECEP /* all eTSEC's Emergency priority */
97 		(CONFIG_SYS_SPCR_TSECEP << SPCR_TSECEP_SHIFT) |
98 #endif
99 #ifdef CONFIG_SYS_SPCR_TSEC1EP /* TSEC1 Emergency priority */
100 		(CONFIG_SYS_SPCR_TSEC1EP << SPCR_TSEC1EP_SHIFT) |
101 #endif
102 #ifdef CONFIG_SYS_SPCR_TSEC2EP /* TSEC2 Emergency priority */
103 		(CONFIG_SYS_SPCR_TSEC2EP << SPCR_TSEC2EP_SHIFT) |
104 #endif
105 		0;
106 	__be32 sccr_mask =
107 #ifdef CONFIG_SYS_SCCR_ENCCM /* Encryption clock mode */
108 		SCCR_ENCCM |
109 #endif
110 #ifdef CONFIG_SYS_SCCR_PCICM /* PCI & DMA clock mode */
111 		SCCR_PCICM |
112 #endif
113 #ifdef CONFIG_SYS_SCCR_PCIEXP1CM	/* PCIE1 clock mode */
114 		SCCR_PCIEXP1CM |
115 #endif
116 #ifdef CONFIG_SYS_SCCR_PCIEXP2CM	/* PCIE2 clock mode */
117 		SCCR_PCIEXP2CM |
118 #endif
119 #ifdef CONFIG_SYS_SCCR_TSECCM /* all TSEC's clock mode */
120 		SCCR_TSECCM |
121 #endif
122 #ifdef CONFIG_SYS_SCCR_TSEC1CM /* TSEC1 clock mode */
123 		SCCR_TSEC1CM |
124 #endif
125 #ifdef CONFIG_SYS_SCCR_TSEC2CM /* TSEC2 clock mode */
126 		SCCR_TSEC2CM |
127 #endif
128 #ifdef CONFIG_SYS_SCCR_TSEC1ON /* TSEC1 clock switch */
129 		SCCR_TSEC1ON |
130 #endif
131 #ifdef CONFIG_SYS_SCCR_TSEC2ON /* TSEC2 clock switch */
132 		SCCR_TSEC2ON |
133 #endif
134 #ifdef CONFIG_SYS_SCCR_USBMPHCM /* USB MPH clock mode */
135 		SCCR_USBMPHCM |
136 #endif
137 #ifdef CONFIG_SYS_SCCR_USBDRCM /* USB DR clock mode */
138 		SCCR_USBDRCM |
139 #endif
140 #ifdef CONFIG_SYS_SCCR_SATACM /* SATA controller clock mode */
141 		SCCR_SATACM |
142 #endif
143 		0;
144 	__be32 sccr_val =
145 #ifdef CONFIG_SYS_SCCR_ENCCM /* Encryption clock mode */
146 		(CONFIG_SYS_SCCR_ENCCM << SCCR_ENCCM_SHIFT) |
147 #endif
148 #ifdef CONFIG_SYS_SCCR_PCICM /* PCI & DMA clock mode */
149 		(CONFIG_SYS_SCCR_PCICM << SCCR_PCICM_SHIFT) |
150 #endif
151 #ifdef CONFIG_SYS_SCCR_PCIEXP1CM	/* PCIE1 clock mode */
152 		(CONFIG_SYS_SCCR_PCIEXP1CM << SCCR_PCIEXP1CM_SHIFT) |
153 #endif
154 #ifdef CONFIG_SYS_SCCR_PCIEXP2CM	/* PCIE2 clock mode */
155 		(CONFIG_SYS_SCCR_PCIEXP2CM << SCCR_PCIEXP2CM_SHIFT) |
156 #endif
157 #ifdef CONFIG_SYS_SCCR_TSECCM /* all TSEC's clock mode */
158 		(CONFIG_SYS_SCCR_TSECCM << SCCR_TSECCM_SHIFT) |
159 #endif
160 #ifdef CONFIG_SYS_SCCR_TSEC1CM /* TSEC1 clock mode */
161 		(CONFIG_SYS_SCCR_TSEC1CM << SCCR_TSEC1CM_SHIFT) |
162 #endif
163 #ifdef CONFIG_SYS_SCCR_TSEC2CM /* TSEC2 clock mode */
164 		(CONFIG_SYS_SCCR_TSEC2CM << SCCR_TSEC2CM_SHIFT) |
165 #endif
166 #ifdef CONFIG_SYS_SCCR_TSEC1ON /* TSEC1 clock switch */
167 		(CONFIG_SYS_SCCR_TSEC1ON << SCCR_TSEC1ON_SHIFT) |
168 #endif
169 #ifdef CONFIG_SYS_SCCR_TSEC2ON /* TSEC2 clock switch */
170 		(CONFIG_SYS_SCCR_TSEC2ON << SCCR_TSEC2ON_SHIFT) |
171 #endif
172 #ifdef CONFIG_SYS_SCCR_USBMPHCM /* USB MPH clock mode */
173 		(CONFIG_SYS_SCCR_USBMPHCM << SCCR_USBMPHCM_SHIFT) |
174 #endif
175 #ifdef CONFIG_SYS_SCCR_USBDRCM /* USB DR clock mode */
176 		(CONFIG_SYS_SCCR_USBDRCM << SCCR_USBDRCM_SHIFT) |
177 #endif
178 #ifdef CONFIG_SYS_SCCR_SATACM /* SATA controller clock mode */
179 		(CONFIG_SYS_SCCR_SATACM << SCCR_SATACM_SHIFT) |
180 #endif
181 		0;
182 	__be32 lcrr_mask =
183 #ifdef CONFIG_SYS_LCRR_DBYP /* PLL bypass */
184 		LCRR_DBYP |
185 #endif
186 #ifdef CONFIG_SYS_LCRR_EADC /* external address delay */
187 		LCRR_EADC |
188 #endif
189 #ifdef CONFIG_SYS_LCRR_CLKDIV /* system clock divider */
190 		LCRR_CLKDIV |
191 #endif
192 		0;
193 	__be32 lcrr_val =
194 #ifdef CONFIG_SYS_LCRR_DBYP /* PLL bypass */
195 		CONFIG_SYS_LCRR_DBYP |
196 #endif
197 #ifdef CONFIG_SYS_LCRR_EADC
198 		CONFIG_SYS_LCRR_EADC |
199 #endif
200 #ifdef CONFIG_SYS_LCRR_CLKDIV /* system clock divider */
201 		CONFIG_SYS_LCRR_CLKDIV |
202 #endif
203 		0;
204 
205 	/* Pointer is writable since we allocated a register for it */
206 	gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
207 
208 	/* global data region was cleared in start.S */
209 
210 	/* system performance tweaking */
211 	clrsetbits_be32(&im->arbiter.acr, acr_mask, acr_val);
212 
213 	clrsetbits_be32(&im->sysconf.spcr, spcr_mask, spcr_val);
214 
215 	clrsetbits_be32(&im->clk.sccr, sccr_mask, sccr_val);
216 
217 	/* RSR - Reset Status Register - clear all status (4.6.1.3) */
218 	gd->arch.reset_status = __raw_readl(&im->reset.rsr);
219 	__raw_writel(~(RSR_RES), &im->reset.rsr);
220 
221 	/* AER - Arbiter Event Register - store status */
222 	gd->arch.arbiter_event_attributes = __raw_readl(&im->arbiter.aeatr);
223 	gd->arch.arbiter_event_address = __raw_readl(&im->arbiter.aeadr);
224 
225 	/*
226 	 * RMR - Reset Mode Register
227 	 * contains checkstop reset enable (4.6.1.4)
228 	 */
229 	__raw_writel(RMR_CSRE & (1<<RMR_CSRE_SHIFT), &im->reset.rmr);
230 
231 	/* LCRR - Clock Ratio Register (10.3.1.16)
232 	 * write, read, and isync per MPC8379ERM rev.1 CLKDEV field description
233 	 */
234 	clrsetbits_be32(&im->im_lbc.lcrr, lcrr_mask, lcrr_val);
235 	__raw_readl(&im->im_lbc.lcrr);
236 	isync();
237 
238 	/* Enable Time Base & Decrementer ( so we will have udelay() )*/
239 	setbits_be32(&im->sysconf.spcr, SPCR_TBEN);
240 
241 	/* System General Purpose Register */
242 #ifdef CONFIG_SYS_SICRH
243 #if defined(CONFIG_MPC834x) || defined(CONFIG_MPC8313)
244 	/* regarding to MPC34x manual rev.1 bits 28..29 must be preserved */
245 	__raw_writel((im->sysconf.sicrh & 0x0000000C) | CONFIG_SYS_SICRH,
246 		     &im->sysconf.sicrh);
247 #else
248 	__raw_writel(CONFIG_SYS_SICRH, &im->sysconf.sicrh);
249 #endif
250 #endif
251 #ifdef CONFIG_SYS_SICRL
252 	__raw_writel(CONFIG_SYS_SICRL, &im->sysconf.sicrl);
253 #endif
254 #ifdef CONFIG_SYS_GPR1
255 	__raw_writel(CONFIG_SYS_GPR1, &im->sysconf.gpr1);
256 #endif
257 #ifdef CONFIG_SYS_DDRCDR /* DDR control driver register */
258 	__raw_writel(CONFIG_SYS_DDRCDR, &im->sysconf.ddrcdr);
259 #endif
260 #ifdef CONFIG_SYS_OBIR /* Output buffer impedance register */
261 	__raw_writel(CONFIG_SYS_OBIR, &im->sysconf.obir);
262 #endif
263 
264 #ifdef CONFIG_QE
265 	/* Config QE ioports */
266 	config_qe_ioports();
267 #endif
268 	/* Set up preliminary BR/OR regs */
269 	init_early_memctl_regs();
270 
271 	/* Local Access window setup */
272 #if defined(CONFIG_SYS_LBLAWBAR0_PRELIM) && defined(CONFIG_SYS_LBLAWAR0_PRELIM)
273 	im->sysconf.lblaw[0].bar = CONFIG_SYS_LBLAWBAR0_PRELIM;
274 	im->sysconf.lblaw[0].ar = CONFIG_SYS_LBLAWAR0_PRELIM;
275 #else
276 #error	CONFIG_SYS_LBLAWBAR0_PRELIM & CONFIG_SYS_LBLAWAR0_PRELIM must be defined
277 #endif
278 
279 #if defined(CONFIG_SYS_LBLAWBAR1_PRELIM) && defined(CONFIG_SYS_LBLAWAR1_PRELIM)
280 	im->sysconf.lblaw[1].bar = CONFIG_SYS_LBLAWBAR1_PRELIM;
281 	im->sysconf.lblaw[1].ar = CONFIG_SYS_LBLAWAR1_PRELIM;
282 #endif
283 #if defined(CONFIG_SYS_LBLAWBAR2_PRELIM) && defined(CONFIG_SYS_LBLAWAR2_PRELIM)
284 	im->sysconf.lblaw[2].bar = CONFIG_SYS_LBLAWBAR2_PRELIM;
285 	im->sysconf.lblaw[2].ar = CONFIG_SYS_LBLAWAR2_PRELIM;
286 #endif
287 #if defined(CONFIG_SYS_LBLAWBAR3_PRELIM) && defined(CONFIG_SYS_LBLAWAR3_PRELIM)
288 	im->sysconf.lblaw[3].bar = CONFIG_SYS_LBLAWBAR3_PRELIM;
289 	im->sysconf.lblaw[3].ar = CONFIG_SYS_LBLAWAR3_PRELIM;
290 #endif
291 #if defined(CONFIG_SYS_LBLAWBAR4_PRELIM) && defined(CONFIG_SYS_LBLAWAR4_PRELIM)
292 	im->sysconf.lblaw[4].bar = CONFIG_SYS_LBLAWBAR4_PRELIM;
293 	im->sysconf.lblaw[4].ar = CONFIG_SYS_LBLAWAR4_PRELIM;
294 #endif
295 #if defined(CONFIG_SYS_LBLAWBAR5_PRELIM) && defined(CONFIG_SYS_LBLAWAR5_PRELIM)
296 	im->sysconf.lblaw[5].bar = CONFIG_SYS_LBLAWBAR5_PRELIM;
297 	im->sysconf.lblaw[5].ar = CONFIG_SYS_LBLAWAR5_PRELIM;
298 #endif
299 #if defined(CONFIG_SYS_LBLAWBAR6_PRELIM) && defined(CONFIG_SYS_LBLAWAR6_PRELIM)
300 	im->sysconf.lblaw[6].bar = CONFIG_SYS_LBLAWBAR6_PRELIM;
301 	im->sysconf.lblaw[6].ar = CONFIG_SYS_LBLAWAR6_PRELIM;
302 #endif
303 #if defined(CONFIG_SYS_LBLAWBAR7_PRELIM) && defined(CONFIG_SYS_LBLAWAR7_PRELIM)
304 	im->sysconf.lblaw[7].bar = CONFIG_SYS_LBLAWBAR7_PRELIM;
305 	im->sysconf.lblaw[7].ar = CONFIG_SYS_LBLAWAR7_PRELIM;
306 #endif
307 #ifdef CONFIG_SYS_GPIO1_PRELIM
308 	im->gpio[0].dat = CONFIG_SYS_GPIO1_DAT;
309 	im->gpio[0].dir = CONFIG_SYS_GPIO1_DIR;
310 #endif
311 #ifdef CONFIG_SYS_GPIO2_PRELIM
312 	im->gpio[1].dat = CONFIG_SYS_GPIO2_DAT;
313 	im->gpio[1].dir = CONFIG_SYS_GPIO2_DIR;
314 #endif
315 #if defined(CONFIG_USB_EHCI_FSL) && defined(CONFIG_MPC831x)
316 	uint32_t temp;
317 	struct usb_ehci *ehci = (struct usb_ehci *)CONFIG_SYS_FSL_USB1_ADDR;
318 
319 	/* Configure interface. */
320 	setbits_be32(&ehci->control, REFSEL_16MHZ | UTMI_PHY_EN);
321 
322 	/* Wait for clock to stabilize */
323 	do {
324 		temp = __raw_readl(&ehci->control);
325 		udelay(1000);
326 	} while (!(temp & PHY_CLK_VALID));
327 #endif
328 }
329 
330 int cpu_init_r (void)
331 {
332 #ifdef CONFIG_QE
333 	uint qe_base = CONFIG_SYS_IMMR + 0x00100000; /* QE immr base */
334 
335 	qe_init(qe_base);
336 	qe_reset();
337 #endif
338 	return 0;
339 }
340 
341 /*
342  * Print out the bus arbiter event
343  */
344 #if defined(CONFIG_DISPLAY_AER_FULL)
345 static int print_83xx_arb_event(int force)
346 {
347 	static char* event[] = {
348 		"Address Time Out",
349 		"Data Time Out",
350 		"Address Only Transfer Type",
351 		"External Control Word Transfer Type",
352 		"Reserved Transfer Type",
353 		"Transfer Error",
354 		"reserved",
355 		"reserved"
356 	};
357 	static char* master[] = {
358 		"e300 Core Data Transaction",
359 		"reserved",
360 		"e300 Core Instruction Fetch",
361 		"reserved",
362 		"TSEC1",
363 		"TSEC2",
364 		"USB MPH",
365 		"USB DR",
366 		"Encryption Core",
367 		"I2C Boot Sequencer",
368 		"JTAG",
369 		"reserved",
370 		"eSDHC",
371 		"PCI1",
372 		"PCI2",
373 		"DMA",
374 		"QUICC Engine 00",
375 		"QUICC Engine 01",
376 		"QUICC Engine 10",
377 		"QUICC Engine 11",
378 		"reserved",
379 		"reserved",
380 		"reserved",
381 		"reserved",
382 		"SATA1",
383 		"SATA2",
384 		"SATA3",
385 		"SATA4",
386 		"reserved",
387 		"PCI Express 1",
388 		"PCI Express 2",
389 		"TDM-DMAC"
390 	};
391 	static char *transfer[] = {
392 		"Address-only, Clean Block",
393 		"Address-only, lwarx reservation set",
394 		"Single-beat or Burst write",
395 		"reserved",
396 		"Address-only, Flush Block",
397 		"reserved",
398 		"Burst write",
399 		"reserved",
400 		"Address-only, sync",
401 		"Address-only, tlbsync",
402 		"Single-beat or Burst read",
403 		"Single-beat or Burst read",
404 		"Address-only, Kill Block",
405 		"Address-only, icbi",
406 		"Burst read",
407 		"reserved",
408 		"Address-only, eieio",
409 		"reserved",
410 		"Single-beat write",
411 		"reserved",
412 		"ecowx - Illegal single-beat write",
413 		"reserved",
414 		"reserved",
415 		"reserved",
416 		"Address-only, TLB Invalidate",
417 		"reserved",
418 		"Single-beat or Burst read",
419 		"reserved",
420 		"eciwx - Illegal single-beat read",
421 		"reserved",
422 		"Burst read",
423 		"reserved"
424 	};
425 
426 	int etype = (gd->arch.arbiter_event_attributes & AEATR_EVENT)
427 		    >> AEATR_EVENT_SHIFT;
428 	int mstr_id = (gd->arch.arbiter_event_attributes & AEATR_MSTR_ID)
429 		      >> AEATR_MSTR_ID_SHIFT;
430 	int tbst = (gd->arch.arbiter_event_attributes & AEATR_TBST)
431 		   >> AEATR_TBST_SHIFT;
432 	int tsize = (gd->arch.arbiter_event_attributes & AEATR_TSIZE)
433 		    >> AEATR_TSIZE_SHIFT;
434 	int ttype = (gd->arch.arbiter_event_attributes & AEATR_TTYPE)
435 		    >> AEATR_TTYPE_SHIFT;
436 
437 	if (!force && !gd->arch.arbiter_event_address)
438 		return 0;
439 
440 	puts("Arbiter Event Status:\n");
441 	printf("       Event Address: 0x%08lX\n",
442 	       gd->arch.arbiter_event_address);
443 	printf("       Event Type:    0x%1x  = %s\n", etype, event[etype]);
444 	printf("       Master ID:     0x%02x = %s\n", mstr_id, master[mstr_id]);
445 	printf("       Transfer Size: 0x%1x  = %d bytes\n", (tbst<<3) | tsize,
446 				tbst ? (tsize ? tsize : 8) : 16 + 8 * tsize);
447 	printf("       Transfer Type: 0x%02x = %s\n", ttype, transfer[ttype]);
448 
449 	return gd->arch.arbiter_event_address;
450 }
451 
452 #elif defined(CONFIG_DISPLAY_AER_BRIEF)
453 
454 static int print_83xx_arb_event(int force)
455 {
456 	if (!force && !gd->arch.arbiter_event_address)
457 		return 0;
458 
459 	printf("Arbiter Event Status: AEATR=0x%08lX, AEADR=0x%08lX\n",
460 		gd->arch.arbiter_event_attributes,
461 		gd->arch.arbiter_event_address);
462 
463 	return gd->arch.arbiter_event_address;
464 }
465 #endif /* CONFIG_DISPLAY_AER_xxxx */
466 
467 /*
468  * Figure out the cause of the reset
469  */
470 int prt_83xx_rsr(void)
471 {
472 	static struct {
473 		ulong mask;
474 		char *desc;
475 	} bits[] = {
476 		{
477 		RSR_SWSR, "Software Soft"}, {
478 		RSR_SWHR, "Software Hard"}, {
479 		RSR_JSRS, "JTAG Soft"}, {
480 		RSR_CSHR, "Check Stop"}, {
481 		RSR_SWRS, "Software Watchdog"}, {
482 		RSR_BMRS, "Bus Monitor"}, {
483 		RSR_SRS,  "External/Internal Soft"}, {
484 		RSR_HRS,  "External/Internal Hard"}
485 	};
486 	static int n = ARRAY_SIZE(bits);
487 	ulong rsr = gd->arch.reset_status;
488 	int i;
489 	char *sep;
490 
491 	puts("Reset Status:");
492 
493 	sep = " ";
494 	for (i = 0; i < n; i++)
495 		if (rsr & bits[i].mask) {
496 			printf("%s%s", sep, bits[i].desc);
497 			sep = ", ";
498 		}
499 	puts("\n");
500 
501 #if defined(CONFIG_DISPLAY_AER_FULL) || defined(CONFIG_DISPLAY_AER_BRIEF)
502 	print_83xx_arb_event(rsr & RSR_BMRS);
503 #endif
504 	puts("\n");
505 
506 	return 0;
507 }
508