1 /* 2 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 /* 24 * CPU specific code for the MPC83xx family. 25 * 26 * Derived from the MPC8260 and MPC85xx. 27 */ 28 29 #include <common.h> 30 #include <watchdog.h> 31 #include <command.h> 32 #include <mpc83xx.h> 33 #include <asm/processor.h> 34 #include <libfdt.h> 35 #include <tsec.h> 36 #include <netdev.h> 37 #include <fsl_esdhc.h> 38 #ifdef CONFIG_BOOTCOUNT_LIMIT 39 #include <asm/immap_qe.h> 40 #include <asm/io.h> 41 #endif 42 43 DECLARE_GLOBAL_DATA_PTR; 44 45 int checkcpu(void) 46 { 47 volatile immap_t *immr; 48 ulong clock = gd->cpu_clk; 49 u32 pvr = get_pvr(); 50 u32 spridr; 51 char buf[32]; 52 int i; 53 54 const struct cpu_type { 55 char name[15]; 56 u32 partid; 57 } cpu_type_list [] = { 58 CPU_TYPE_ENTRY(8311), 59 CPU_TYPE_ENTRY(8313), 60 CPU_TYPE_ENTRY(8314), 61 CPU_TYPE_ENTRY(8315), 62 CPU_TYPE_ENTRY(8321), 63 CPU_TYPE_ENTRY(8323), 64 CPU_TYPE_ENTRY(8343), 65 CPU_TYPE_ENTRY(8347_TBGA_), 66 CPU_TYPE_ENTRY(8347_PBGA_), 67 CPU_TYPE_ENTRY(8349), 68 CPU_TYPE_ENTRY(8358_TBGA_), 69 CPU_TYPE_ENTRY(8358_PBGA_), 70 CPU_TYPE_ENTRY(8360), 71 CPU_TYPE_ENTRY(8377), 72 CPU_TYPE_ENTRY(8378), 73 CPU_TYPE_ENTRY(8379), 74 }; 75 76 immr = (immap_t *)CONFIG_SYS_IMMR; 77 78 puts("CPU: "); 79 80 switch (pvr & 0xffff0000) { 81 case PVR_E300C1: 82 printf("e300c1, "); 83 break; 84 85 case PVR_E300C2: 86 printf("e300c2, "); 87 break; 88 89 case PVR_E300C3: 90 printf("e300c3, "); 91 break; 92 93 case PVR_E300C4: 94 printf("e300c4, "); 95 break; 96 97 default: 98 printf("Unknown core, "); 99 } 100 101 spridr = immr->sysconf.spridr; 102 103 for (i = 0; i < ARRAY_SIZE(cpu_type_list); i++) 104 if (cpu_type_list[i].partid == PARTID_NO_E(spridr)) { 105 puts("MPC"); 106 puts(cpu_type_list[i].name); 107 if (IS_E_PROCESSOR(spridr)) 108 puts("E"); 109 if (REVID_MAJOR(spridr) >= 2) 110 puts("A"); 111 printf(", Rev: %d.%d", REVID_MAJOR(spridr), 112 REVID_MINOR(spridr)); 113 break; 114 } 115 116 if (i == ARRAY_SIZE(cpu_type_list)) 117 printf("(SPRIDR %08x unknown), ", spridr); 118 119 printf(" at %s MHz, ", strmhz(buf, clock)); 120 121 printf("CSB: %s MHz\n", strmhz(buf, gd->csb_clk)); 122 123 return 0; 124 } 125 126 127 /* 128 * Program a UPM with the code supplied in the table. 129 * 130 * The 'dummy' variable is used to increment the MAD. 'dummy' is 131 * supposed to be a pointer to the memory of the device being 132 * programmed by the UPM. The data in the MDR is written into 133 * memory and the MAD is incremented every time there's a write 134 * to 'dummy'. Unfortunately, the current prototype for this 135 * function doesn't allow for passing the address of this 136 * device, and changing the prototype will break a number lots 137 * of other code, so we need to use a round-about way of finding 138 * the value for 'dummy'. 139 * 140 * The value can be extracted from the base address bits of the 141 * Base Register (BR) associated with the specific UPM. To find 142 * that BR, we need to scan all 8 BRs until we find the one that 143 * has its MSEL bits matching the UPM we want. Once we know the 144 * right BR, we can extract the base address bits from it. 145 * 146 * The MxMR and the BR and OR of the chosen bank should all be 147 * configured before calling this function. 148 * 149 * Parameters: 150 * upm: 0=UPMA, 1=UPMB, 2=UPMC 151 * table: Pointer to an array of values to program 152 * size: Number of elements in the array. Must be 64 or less. 153 */ 154 void upmconfig (uint upm, uint *table, uint size) 155 { 156 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; 157 volatile fsl_lbus_t *lbus = &immap->lbus; 158 volatile uchar *dummy = NULL; 159 const u32 msel = (upm + 4) << BR_MSEL_SHIFT; /* What the MSEL field in BRn should be */ 160 volatile u32 *mxmr = &lbus->mamr + upm; /* Pointer to mamr, mbmr, or mcmr */ 161 uint i; 162 163 /* Scan all the banks to determine the base address of the device */ 164 for (i = 0; i < 8; i++) { 165 if ((lbus->bank[i].br & BR_MSEL) == msel) { 166 dummy = (uchar *) (lbus->bank[i].br & BR_BA); 167 break; 168 } 169 } 170 171 if (!dummy) { 172 printf("Error: %s() could not find matching BR\n", __FUNCTION__); 173 hang(); 174 } 175 176 /* Set the OP field in the MxMR to "write" and the MAD field to 000000 */ 177 *mxmr = (*mxmr & 0xCFFFFFC0) | 0x10000000; 178 179 for (i = 0; i < size; i++) { 180 lbus->mdr = table[i]; 181 __asm__ __volatile__ ("sync"); 182 *dummy = 0; /* Write the value to memory and increment MAD */ 183 __asm__ __volatile__ ("sync"); 184 while(((*mxmr & 0x3f) != ((i + 1) & 0x3f))); 185 } 186 187 /* Set the OP field in the MxMR to "normal" and the MAD field to 000000 */ 188 *mxmr &= 0xCFFFFFC0; 189 } 190 191 192 int 193 do_reset (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) 194 { 195 ulong msr; 196 #ifndef MPC83xx_RESET 197 ulong addr; 198 #endif 199 200 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; 201 202 puts("Resetting the board.\n"); 203 204 #ifdef MPC83xx_RESET 205 206 /* Interrupts and MMU off */ 207 __asm__ __volatile__ ("mfmsr %0":"=r" (msr):); 208 209 msr &= ~( MSR_EE | MSR_IR | MSR_DR); 210 __asm__ __volatile__ ("mtmsr %0"::"r" (msr)); 211 212 /* enable Reset Control Reg */ 213 immap->reset.rpr = 0x52535445; 214 __asm__ __volatile__ ("sync"); 215 __asm__ __volatile__ ("isync"); 216 217 /* confirm Reset Control Reg is enabled */ 218 while(!((immap->reset.rcer) & RCER_CRE)); 219 220 udelay(200); 221 222 /* perform reset, only one bit */ 223 immap->reset.rcr = RCR_SWHR; 224 225 #else /* ! MPC83xx_RESET */ 226 227 immap->reset.rmr = RMR_CSRE; /* Checkstop Reset enable */ 228 229 /* Interrupts and MMU off */ 230 __asm__ __volatile__ ("mfmsr %0":"=r" (msr):); 231 232 msr &= ~(MSR_ME | MSR_EE | MSR_IR | MSR_DR); 233 __asm__ __volatile__ ("mtmsr %0"::"r" (msr)); 234 235 /* 236 * Trying to execute the next instruction at a non-existing address 237 * should cause a machine check, resulting in reset 238 */ 239 addr = CONFIG_SYS_RESET_ADDRESS; 240 241 ((void (*)(void)) addr) (); 242 #endif /* MPC83xx_RESET */ 243 244 return 1; 245 } 246 247 248 /* 249 * Get timebase clock frequency (like cpu_clk in Hz) 250 */ 251 252 unsigned long get_tbclk(void) 253 { 254 ulong tbclk; 255 256 tbclk = (gd->bus_clk + 3L) / 4L; 257 258 return tbclk; 259 } 260 261 262 #if defined(CONFIG_WATCHDOG) 263 void watchdog_reset (void) 264 { 265 int re_enable = disable_interrupts(); 266 267 /* Reset the 83xx watchdog */ 268 volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; 269 immr->wdt.swsrr = 0x556c; 270 immr->wdt.swsrr = 0xaa39; 271 272 if (re_enable) 273 enable_interrupts (); 274 } 275 #endif 276 277 /* 278 * Initializes on-chip ethernet controllers. 279 * to override, implement board_eth_init() 280 */ 281 int cpu_eth_init(bd_t *bis) 282 { 283 #if defined(CONFIG_UEC_ETH) 284 uec_standard_init(bis); 285 #endif 286 287 #if defined(CONFIG_TSEC_ENET) 288 tsec_standard_init(bis); 289 #endif 290 return 0; 291 } 292 293 /* 294 * Initializes on-chip MMC controllers. 295 * to override, implement board_mmc_init() 296 */ 297 int cpu_mmc_init(bd_t *bis) 298 { 299 #ifdef CONFIG_FSL_ESDHC 300 return fsl_esdhc_mmc_init(bis); 301 #else 302 return 0; 303 #endif 304 } 305 306 #ifdef CONFIG_BOOTCOUNT_LIMIT 307 308 #if !defined(CONFIG_MPC8360) 309 #error "CONFIG_BOOTCOUNT_LIMIT only for MPC8360 implemented" 310 #endif 311 312 #if !defined(CONFIG_BOOTCOUNT_ADDR) 313 #define CONFIG_BOOTCOUNT_ADDR (0x110000 + QE_MURAM_SIZE - 2 * sizeof(unsigned long)) 314 #endif 315 316 #include <asm/io.h> 317 318 void bootcount_store (ulong a) 319 { 320 void *reg = (void *)(CONFIG_SYS_IMMR + CONFIG_BOOTCOUNT_ADDR); 321 out_be32 (reg, a); 322 out_be32 (reg + 4, BOOTCOUNT_MAGIC); 323 } 324 325 ulong bootcount_load (void) 326 { 327 void *reg = (void *)(CONFIG_SYS_IMMR + CONFIG_BOOTCOUNT_ADDR); 328 329 if (in_be32 (reg + 4) != BOOTCOUNT_MAGIC) 330 return 0; 331 else 332 return in_be32 (reg); 333 } 334 #endif /* CONFIG_BOOTCOUNT_LIMIT */ 335