1 /* 2 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 /* 24 * CPU specific code for the MPC83xx family. 25 * 26 * Derived from the MPC8260 and MPC85xx. 27 */ 28 29 #include <common.h> 30 #include <watchdog.h> 31 #include <command.h> 32 #include <mpc83xx.h> 33 #include <asm/processor.h> 34 #include <libfdt.h> 35 #include <tsec.h> 36 #include <netdev.h> 37 #include <fsl_esdhc.h> 38 #ifdef CONFIG_BOOTCOUNT_LIMIT 39 #include <asm/immap_qe.h> 40 #include <asm/io.h> 41 #endif 42 43 DECLARE_GLOBAL_DATA_PTR; 44 45 int checkcpu(void) 46 { 47 volatile immap_t *immr; 48 ulong clock = gd->cpu_clk; 49 u32 pvr = get_pvr(); 50 u32 spridr; 51 char buf[32]; 52 int i; 53 54 const struct cpu_type { 55 char name[15]; 56 u32 partid; 57 } cpu_type_list [] = { 58 CPU_TYPE_ENTRY(8308), 59 CPU_TYPE_ENTRY(8309), 60 CPU_TYPE_ENTRY(8311), 61 CPU_TYPE_ENTRY(8313), 62 CPU_TYPE_ENTRY(8314), 63 CPU_TYPE_ENTRY(8315), 64 CPU_TYPE_ENTRY(8321), 65 CPU_TYPE_ENTRY(8323), 66 CPU_TYPE_ENTRY(8343), 67 CPU_TYPE_ENTRY(8347_TBGA_), 68 CPU_TYPE_ENTRY(8347_PBGA_), 69 CPU_TYPE_ENTRY(8349), 70 CPU_TYPE_ENTRY(8358_TBGA_), 71 CPU_TYPE_ENTRY(8358_PBGA_), 72 CPU_TYPE_ENTRY(8360), 73 CPU_TYPE_ENTRY(8377), 74 CPU_TYPE_ENTRY(8378), 75 CPU_TYPE_ENTRY(8379), 76 }; 77 78 immr = (immap_t *)CONFIG_SYS_IMMR; 79 80 puts("CPU: "); 81 82 switch (pvr & 0xffff0000) { 83 case PVR_E300C1: 84 printf("e300c1, "); 85 break; 86 87 case PVR_E300C2: 88 printf("e300c2, "); 89 break; 90 91 case PVR_E300C3: 92 printf("e300c3, "); 93 break; 94 95 case PVR_E300C4: 96 printf("e300c4, "); 97 break; 98 99 default: 100 printf("Unknown core, "); 101 } 102 103 spridr = immr->sysconf.spridr; 104 105 for (i = 0; i < ARRAY_SIZE(cpu_type_list); i++) 106 if (cpu_type_list[i].partid == PARTID_NO_E(spridr)) { 107 puts("MPC"); 108 puts(cpu_type_list[i].name); 109 if (IS_E_PROCESSOR(spridr)) 110 puts("E"); 111 if ((SPR_FAMILY(spridr) == SPR_834X_FAMILY || 112 SPR_FAMILY(spridr) == SPR_836X_FAMILY) && 113 REVID_MAJOR(spridr) >= 2) 114 puts("A"); 115 printf(", Rev: %d.%d", REVID_MAJOR(spridr), 116 REVID_MINOR(spridr)); 117 break; 118 } 119 120 if (i == ARRAY_SIZE(cpu_type_list)) 121 printf("(SPRIDR %08x unknown), ", spridr); 122 123 printf(" at %s MHz, ", strmhz(buf, clock)); 124 125 printf("CSB: %s MHz\n", strmhz(buf, gd->csb_clk)); 126 127 return 0; 128 } 129 130 int 131 do_reset (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) 132 { 133 ulong msr; 134 #ifndef MPC83xx_RESET 135 ulong addr; 136 #endif 137 138 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; 139 140 puts("Resetting the board.\n"); 141 142 #ifdef MPC83xx_RESET 143 144 /* Interrupts and MMU off */ 145 __asm__ __volatile__ ("mfmsr %0":"=r" (msr):); 146 147 msr &= ~( MSR_EE | MSR_IR | MSR_DR); 148 __asm__ __volatile__ ("mtmsr %0"::"r" (msr)); 149 150 /* enable Reset Control Reg */ 151 immap->reset.rpr = 0x52535445; 152 __asm__ __volatile__ ("sync"); 153 __asm__ __volatile__ ("isync"); 154 155 /* confirm Reset Control Reg is enabled */ 156 while(!((immap->reset.rcer) & RCER_CRE)); 157 158 udelay(200); 159 160 /* perform reset, only one bit */ 161 immap->reset.rcr = RCR_SWHR; 162 163 #else /* ! MPC83xx_RESET */ 164 165 immap->reset.rmr = RMR_CSRE; /* Checkstop Reset enable */ 166 167 /* Interrupts and MMU off */ 168 __asm__ __volatile__ ("mfmsr %0":"=r" (msr):); 169 170 msr &= ~(MSR_ME | MSR_EE | MSR_IR | MSR_DR); 171 __asm__ __volatile__ ("mtmsr %0"::"r" (msr)); 172 173 /* 174 * Trying to execute the next instruction at a non-existing address 175 * should cause a machine check, resulting in reset 176 */ 177 addr = CONFIG_SYS_RESET_ADDRESS; 178 179 ((void (*)(void)) addr) (); 180 #endif /* MPC83xx_RESET */ 181 182 return 1; 183 } 184 185 186 /* 187 * Get timebase clock frequency (like cpu_clk in Hz) 188 */ 189 190 unsigned long get_tbclk(void) 191 { 192 ulong tbclk; 193 194 tbclk = (gd->bus_clk + 3L) / 4L; 195 196 return tbclk; 197 } 198 199 200 #if defined(CONFIG_WATCHDOG) 201 void watchdog_reset (void) 202 { 203 int re_enable = disable_interrupts(); 204 205 /* Reset the 83xx watchdog */ 206 volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; 207 immr->wdt.swsrr = 0x556c; 208 immr->wdt.swsrr = 0xaa39; 209 210 if (re_enable) 211 enable_interrupts (); 212 } 213 #endif 214 215 /* 216 * Initializes on-chip ethernet controllers. 217 * to override, implement board_eth_init() 218 */ 219 int cpu_eth_init(bd_t *bis) 220 { 221 #if defined(CONFIG_UEC_ETH) 222 uec_standard_init(bis); 223 #endif 224 225 #if defined(CONFIG_TSEC_ENET) 226 tsec_standard_init(bis); 227 #endif 228 return 0; 229 } 230 231 /* 232 * Initializes on-chip MMC controllers. 233 * to override, implement board_mmc_init() 234 */ 235 int cpu_mmc_init(bd_t *bis) 236 { 237 #ifdef CONFIG_FSL_ESDHC 238 return fsl_esdhc_mmc_init(bis); 239 #else 240 return 0; 241 #endif 242 } 243