1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. 4 */ 5 6 /* 7 * CPU specific code for the MPC83xx family. 8 * 9 * Derived from the MPC8260 and MPC85xx. 10 */ 11 12 #include <common.h> 13 #include <watchdog.h> 14 #include <command.h> 15 #include <mpc83xx.h> 16 #include <asm/processor.h> 17 #include <linux/libfdt.h> 18 #include <tsec.h> 19 #include <netdev.h> 20 #include <fsl_esdhc.h> 21 #if defined(CONFIG_BOOTCOUNT_LIMIT) && !defined(CONFIG_MPC831x) 22 #include <linux/immap_qe.h> 23 #include <asm/io.h> 24 #endif 25 26 DECLARE_GLOBAL_DATA_PTR; 27 28 #ifndef CONFIG_CPU_MPC83XX 29 int checkcpu(void) 30 { 31 volatile immap_t *immr; 32 ulong clock = gd->cpu_clk; 33 u32 pvr = get_pvr(); 34 u32 spridr; 35 char buf[32]; 36 int ret; 37 int i; 38 39 const struct cpu_type { 40 char name[15]; 41 u32 partid; 42 } cpu_type_list [] = { 43 CPU_TYPE_ENTRY(8308), 44 CPU_TYPE_ENTRY(8309), 45 CPU_TYPE_ENTRY(8311), 46 CPU_TYPE_ENTRY(8313), 47 CPU_TYPE_ENTRY(8314), 48 CPU_TYPE_ENTRY(8315), 49 CPU_TYPE_ENTRY(8321), 50 CPU_TYPE_ENTRY(8323), 51 CPU_TYPE_ENTRY(8343), 52 CPU_TYPE_ENTRY(8347_TBGA_), 53 CPU_TYPE_ENTRY(8347_PBGA_), 54 CPU_TYPE_ENTRY(8349), 55 CPU_TYPE_ENTRY(8358_TBGA_), 56 CPU_TYPE_ENTRY(8358_PBGA_), 57 CPU_TYPE_ENTRY(8360), 58 CPU_TYPE_ENTRY(8377), 59 CPU_TYPE_ENTRY(8378), 60 CPU_TYPE_ENTRY(8379), 61 }; 62 63 immr = (immap_t *)CONFIG_SYS_IMMR; 64 65 ret = prt_83xx_rsr(); 66 if (ret) 67 return ret; 68 69 puts("CPU: "); 70 71 switch (pvr & 0xffff0000) { 72 case PVR_E300C1: 73 printf("e300c1, "); 74 break; 75 76 case PVR_E300C2: 77 printf("e300c2, "); 78 break; 79 80 case PVR_E300C3: 81 printf("e300c3, "); 82 break; 83 84 case PVR_E300C4: 85 printf("e300c4, "); 86 break; 87 88 default: 89 printf("Unknown core, "); 90 } 91 92 spridr = immr->sysconf.spridr; 93 94 for (i = 0; i < ARRAY_SIZE(cpu_type_list); i++) 95 if (cpu_type_list[i].partid == PARTID_NO_E(spridr)) { 96 puts("MPC"); 97 puts(cpu_type_list[i].name); 98 if (IS_E_PROCESSOR(spridr)) 99 puts("E"); 100 if ((SPR_FAMILY(spridr) == SPR_834X_FAMILY || 101 SPR_FAMILY(spridr) == SPR_836X_FAMILY) && 102 REVID_MAJOR(spridr) >= 2) 103 puts("A"); 104 printf(", Rev: %d.%d", REVID_MAJOR(spridr), 105 REVID_MINOR(spridr)); 106 break; 107 } 108 109 if (i == ARRAY_SIZE(cpu_type_list)) 110 printf("(SPRIDR %08x unknown), ", spridr); 111 112 printf(" at %s MHz, ", strmhz(buf, clock)); 113 114 printf("CSB: %s MHz\n", strmhz(buf, gd->arch.csb_clk)); 115 116 return 0; 117 } 118 #endif 119 120 #ifndef CONFIG_SYSRESET 121 int 122 do_reset (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) 123 { 124 ulong msr; 125 #ifndef MPC83xx_RESET 126 ulong addr; 127 #endif 128 129 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; 130 131 puts("Resetting the board.\n"); 132 133 #ifdef MPC83xx_RESET 134 135 /* Interrupts and MMU off */ 136 __asm__ __volatile__ ("mfmsr %0":"=r" (msr):); 137 138 msr &= ~( MSR_EE | MSR_IR | MSR_DR); 139 __asm__ __volatile__ ("mtmsr %0"::"r" (msr)); 140 141 /* enable Reset Control Reg */ 142 immap->reset.rpr = 0x52535445; 143 __asm__ __volatile__ ("sync"); 144 __asm__ __volatile__ ("isync"); 145 146 /* confirm Reset Control Reg is enabled */ 147 while(!((immap->reset.rcer) & RCER_CRE)); 148 149 udelay(200); 150 151 /* perform reset, only one bit */ 152 immap->reset.rcr = RCR_SWHR; 153 154 #else /* ! MPC83xx_RESET */ 155 156 immap->reset.rmr = RMR_CSRE; /* Checkstop Reset enable */ 157 158 /* Interrupts and MMU off */ 159 __asm__ __volatile__ ("mfmsr %0":"=r" (msr):); 160 161 msr &= ~(MSR_ME | MSR_EE | MSR_IR | MSR_DR); 162 __asm__ __volatile__ ("mtmsr %0"::"r" (msr)); 163 164 /* 165 * Trying to execute the next instruction at a non-existing address 166 * should cause a machine check, resulting in reset 167 */ 168 addr = CONFIG_SYS_RESET_ADDRESS; 169 170 ((void (*)(void)) addr) (); 171 #endif /* MPC83xx_RESET */ 172 173 return 1; 174 } 175 #endif 176 177 /* 178 * Get timebase clock frequency (like cpu_clk in Hz) 179 */ 180 #ifndef CONFIG_TIMER 181 unsigned long get_tbclk(void) 182 { 183 return (gd->bus_clk + 3L) / 4L; 184 } 185 #endif 186 187 #if defined(CONFIG_WATCHDOG) 188 void watchdog_reset (void) 189 { 190 int re_enable = disable_interrupts(); 191 192 /* Reset the 83xx watchdog */ 193 volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; 194 immr->wdt.swsrr = 0x556c; 195 immr->wdt.swsrr = 0xaa39; 196 197 if (re_enable) 198 enable_interrupts (); 199 } 200 #endif 201 202 /* 203 * Initializes on-chip ethernet controllers. 204 * to override, implement board_eth_init() 205 */ 206 int cpu_eth_init(bd_t *bis) 207 { 208 #if defined(CONFIG_UEC_ETH) 209 uec_standard_init(bis); 210 #endif 211 212 #if defined(CONFIG_TSEC_ENET) 213 tsec_standard_init(bis); 214 #endif 215 return 0; 216 } 217 218 /* 219 * Initializes on-chip MMC controllers. 220 * to override, implement board_mmc_init() 221 */ 222 int cpu_mmc_init(bd_t *bis) 223 { 224 #ifdef CONFIG_FSL_ESDHC 225 return fsl_esdhc_mmc_init(bis); 226 #else 227 return 0; 228 #endif 229 } 230