1 /* 2 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 /* 24 * CPU specific code for the MPC83xx family. 25 * 26 * Derived from the MPC8260 and MPC85xx. 27 */ 28 29 #include <common.h> 30 #include <watchdog.h> 31 #include <command.h> 32 #include <mpc83xx.h> 33 #include <asm/processor.h> 34 #include <libfdt.h> 35 #include <tsec.h> 36 #include <netdev.h> 37 #include <fsl_esdhc.h> 38 #ifdef CONFIG_BOOTCOUNT_LIMIT 39 #include <asm/immap_qe.h> 40 #include <asm/io.h> 41 #endif 42 43 DECLARE_GLOBAL_DATA_PTR; 44 45 int checkcpu(void) 46 { 47 volatile immap_t *immr; 48 ulong clock = gd->cpu_clk; 49 u32 pvr = get_pvr(); 50 u32 spridr; 51 char buf[32]; 52 int i; 53 54 const struct cpu_type { 55 char name[15]; 56 u32 partid; 57 } cpu_type_list [] = { 58 CPU_TYPE_ENTRY(8311), 59 CPU_TYPE_ENTRY(8313), 60 CPU_TYPE_ENTRY(8314), 61 CPU_TYPE_ENTRY(8315), 62 CPU_TYPE_ENTRY(8321), 63 CPU_TYPE_ENTRY(8323), 64 CPU_TYPE_ENTRY(8343), 65 CPU_TYPE_ENTRY(8347_TBGA_), 66 CPU_TYPE_ENTRY(8347_PBGA_), 67 CPU_TYPE_ENTRY(8349), 68 CPU_TYPE_ENTRY(8358_TBGA_), 69 CPU_TYPE_ENTRY(8358_PBGA_), 70 CPU_TYPE_ENTRY(8360), 71 CPU_TYPE_ENTRY(8377), 72 CPU_TYPE_ENTRY(8378), 73 CPU_TYPE_ENTRY(8379), 74 }; 75 76 immr = (immap_t *)CONFIG_SYS_IMMR; 77 78 puts("CPU: "); 79 80 switch (pvr & 0xffff0000) { 81 case PVR_E300C1: 82 printf("e300c1, "); 83 break; 84 85 case PVR_E300C2: 86 printf("e300c2, "); 87 break; 88 89 case PVR_E300C3: 90 printf("e300c3, "); 91 break; 92 93 case PVR_E300C4: 94 printf("e300c4, "); 95 break; 96 97 default: 98 printf("Unknown core, "); 99 } 100 101 spridr = immr->sysconf.spridr; 102 103 for (i = 0; i < ARRAY_SIZE(cpu_type_list); i++) 104 if (cpu_type_list[i].partid == PARTID_NO_E(spridr)) { 105 puts("MPC"); 106 puts(cpu_type_list[i].name); 107 if (IS_E_PROCESSOR(spridr)) 108 puts("E"); 109 if ((SPR_FAMILY(spridr) == SPR_834X_FAMILY || 110 SPR_FAMILY(spridr) == SPR_836X_FAMILY) && 111 REVID_MAJOR(spridr) >= 2) 112 puts("A"); 113 printf(", Rev: %d.%d", REVID_MAJOR(spridr), 114 REVID_MINOR(spridr)); 115 break; 116 } 117 118 if (i == ARRAY_SIZE(cpu_type_list)) 119 printf("(SPRIDR %08x unknown), ", spridr); 120 121 printf(" at %s MHz, ", strmhz(buf, clock)); 122 123 printf("CSB: %s MHz\n", strmhz(buf, gd->csb_clk)); 124 125 return 0; 126 } 127 128 129 /* 130 * Program a UPM with the code supplied in the table. 131 * 132 * The 'dummy' variable is used to increment the MAD. 'dummy' is 133 * supposed to be a pointer to the memory of the device being 134 * programmed by the UPM. The data in the MDR is written into 135 * memory and the MAD is incremented every time there's a write 136 * to 'dummy'. Unfortunately, the current prototype for this 137 * function doesn't allow for passing the address of this 138 * device, and changing the prototype will break a number lots 139 * of other code, so we need to use a round-about way of finding 140 * the value for 'dummy'. 141 * 142 * The value can be extracted from the base address bits of the 143 * Base Register (BR) associated with the specific UPM. To find 144 * that BR, we need to scan all 8 BRs until we find the one that 145 * has its MSEL bits matching the UPM we want. Once we know the 146 * right BR, we can extract the base address bits from it. 147 * 148 * The MxMR and the BR and OR of the chosen bank should all be 149 * configured before calling this function. 150 * 151 * Parameters: 152 * upm: 0=UPMA, 1=UPMB, 2=UPMC 153 * table: Pointer to an array of values to program 154 * size: Number of elements in the array. Must be 64 or less. 155 */ 156 void upmconfig (uint upm, uint *table, uint size) 157 { 158 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; 159 volatile fsl_lbus_t *lbus = &immap->lbus; 160 volatile uchar *dummy = NULL; 161 const u32 msel = (upm + 4) << BR_MSEL_SHIFT; /* What the MSEL field in BRn should be */ 162 volatile u32 *mxmr = &lbus->mamr + upm; /* Pointer to mamr, mbmr, or mcmr */ 163 uint i; 164 165 /* Scan all the banks to determine the base address of the device */ 166 for (i = 0; i < 8; i++) { 167 if ((lbus->bank[i].br & BR_MSEL) == msel) { 168 dummy = (uchar *) (lbus->bank[i].br & BR_BA); 169 break; 170 } 171 } 172 173 if (!dummy) { 174 printf("Error: %s() could not find matching BR\n", __FUNCTION__); 175 hang(); 176 } 177 178 /* Set the OP field in the MxMR to "write" and the MAD field to 000000 */ 179 *mxmr = (*mxmr & 0xCFFFFFC0) | 0x10000000; 180 181 for (i = 0; i < size; i++) { 182 lbus->mdr = table[i]; 183 __asm__ __volatile__ ("sync"); 184 *dummy = 0; /* Write the value to memory and increment MAD */ 185 __asm__ __volatile__ ("sync"); 186 while(((*mxmr & 0x3f) != ((i + 1) & 0x3f))); 187 } 188 189 /* Set the OP field in the MxMR to "normal" and the MAD field to 000000 */ 190 *mxmr &= 0xCFFFFFC0; 191 } 192 193 194 int 195 do_reset (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) 196 { 197 ulong msr; 198 #ifndef MPC83xx_RESET 199 ulong addr; 200 #endif 201 202 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; 203 204 puts("Resetting the board.\n"); 205 206 #ifdef MPC83xx_RESET 207 208 /* Interrupts and MMU off */ 209 __asm__ __volatile__ ("mfmsr %0":"=r" (msr):); 210 211 msr &= ~( MSR_EE | MSR_IR | MSR_DR); 212 __asm__ __volatile__ ("mtmsr %0"::"r" (msr)); 213 214 /* enable Reset Control Reg */ 215 immap->reset.rpr = 0x52535445; 216 __asm__ __volatile__ ("sync"); 217 __asm__ __volatile__ ("isync"); 218 219 /* confirm Reset Control Reg is enabled */ 220 while(!((immap->reset.rcer) & RCER_CRE)); 221 222 udelay(200); 223 224 /* perform reset, only one bit */ 225 immap->reset.rcr = RCR_SWHR; 226 227 #else /* ! MPC83xx_RESET */ 228 229 immap->reset.rmr = RMR_CSRE; /* Checkstop Reset enable */ 230 231 /* Interrupts and MMU off */ 232 __asm__ __volatile__ ("mfmsr %0":"=r" (msr):); 233 234 msr &= ~(MSR_ME | MSR_EE | MSR_IR | MSR_DR); 235 __asm__ __volatile__ ("mtmsr %0"::"r" (msr)); 236 237 /* 238 * Trying to execute the next instruction at a non-existing address 239 * should cause a machine check, resulting in reset 240 */ 241 addr = CONFIG_SYS_RESET_ADDRESS; 242 243 ((void (*)(void)) addr) (); 244 #endif /* MPC83xx_RESET */ 245 246 return 1; 247 } 248 249 250 /* 251 * Get timebase clock frequency (like cpu_clk in Hz) 252 */ 253 254 unsigned long get_tbclk(void) 255 { 256 ulong tbclk; 257 258 tbclk = (gd->bus_clk + 3L) / 4L; 259 260 return tbclk; 261 } 262 263 264 #if defined(CONFIG_WATCHDOG) 265 void watchdog_reset (void) 266 { 267 int re_enable = disable_interrupts(); 268 269 /* Reset the 83xx watchdog */ 270 volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; 271 immr->wdt.swsrr = 0x556c; 272 immr->wdt.swsrr = 0xaa39; 273 274 if (re_enable) 275 enable_interrupts (); 276 } 277 #endif 278 279 /* 280 * Initializes on-chip ethernet controllers. 281 * to override, implement board_eth_init() 282 */ 283 int cpu_eth_init(bd_t *bis) 284 { 285 #if defined(CONFIG_UEC_ETH) 286 uec_standard_init(bis); 287 #endif 288 289 #if defined(CONFIG_TSEC_ENET) 290 tsec_standard_init(bis); 291 #endif 292 return 0; 293 } 294 295 /* 296 * Initializes on-chip MMC controllers. 297 * to override, implement board_mmc_init() 298 */ 299 int cpu_mmc_init(bd_t *bis) 300 { 301 #ifdef CONFIG_FSL_ESDHC 302 return fsl_esdhc_mmc_init(bis); 303 #else 304 return 0; 305 #endif 306 } 307