1 /* 2 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 /* 24 * CPU specific code for the MPC83xx family. 25 * 26 * Derived from the MPC8260 and MPC85xx. 27 */ 28 29 #include <common.h> 30 #include <watchdog.h> 31 #include <command.h> 32 #include <mpc83xx.h> 33 #include <asm/processor.h> 34 #include <libfdt.h> 35 #include <tsec.h> 36 #include <netdev.h> 37 #include <fsl_esdhc.h> 38 #ifdef CONFIG_BOOTCOUNT_LIMIT 39 #include <asm/immap_qe.h> 40 #include <asm/io.h> 41 #endif 42 43 DECLARE_GLOBAL_DATA_PTR; 44 45 int checkcpu(void) 46 { 47 volatile immap_t *immr; 48 ulong clock = gd->cpu_clk; 49 u32 pvr = get_pvr(); 50 u32 spridr; 51 char buf[32]; 52 int i; 53 54 const struct cpu_type { 55 char name[15]; 56 u32 partid; 57 } cpu_type_list [] = { 58 CPU_TYPE_ENTRY(8308), 59 CPU_TYPE_ENTRY(8311), 60 CPU_TYPE_ENTRY(8313), 61 CPU_TYPE_ENTRY(8314), 62 CPU_TYPE_ENTRY(8315), 63 CPU_TYPE_ENTRY(8321), 64 CPU_TYPE_ENTRY(8323), 65 CPU_TYPE_ENTRY(8343), 66 CPU_TYPE_ENTRY(8347_TBGA_), 67 CPU_TYPE_ENTRY(8347_PBGA_), 68 CPU_TYPE_ENTRY(8349), 69 CPU_TYPE_ENTRY(8358_TBGA_), 70 CPU_TYPE_ENTRY(8358_PBGA_), 71 CPU_TYPE_ENTRY(8360), 72 CPU_TYPE_ENTRY(8377), 73 CPU_TYPE_ENTRY(8378), 74 CPU_TYPE_ENTRY(8379), 75 }; 76 77 immr = (immap_t *)CONFIG_SYS_IMMR; 78 79 puts("CPU: "); 80 81 switch (pvr & 0xffff0000) { 82 case PVR_E300C1: 83 printf("e300c1, "); 84 break; 85 86 case PVR_E300C2: 87 printf("e300c2, "); 88 break; 89 90 case PVR_E300C3: 91 printf("e300c3, "); 92 break; 93 94 case PVR_E300C4: 95 printf("e300c4, "); 96 break; 97 98 default: 99 printf("Unknown core, "); 100 } 101 102 spridr = immr->sysconf.spridr; 103 104 for (i = 0; i < ARRAY_SIZE(cpu_type_list); i++) 105 if (cpu_type_list[i].partid == PARTID_NO_E(spridr)) { 106 puts("MPC"); 107 puts(cpu_type_list[i].name); 108 if (IS_E_PROCESSOR(spridr)) 109 puts("E"); 110 if ((SPR_FAMILY(spridr) == SPR_834X_FAMILY || 111 SPR_FAMILY(spridr) == SPR_836X_FAMILY) && 112 REVID_MAJOR(spridr) >= 2) 113 puts("A"); 114 printf(", Rev: %d.%d", REVID_MAJOR(spridr), 115 REVID_MINOR(spridr)); 116 break; 117 } 118 119 if (i == ARRAY_SIZE(cpu_type_list)) 120 printf("(SPRIDR %08x unknown), ", spridr); 121 122 printf(" at %s MHz, ", strmhz(buf, clock)); 123 124 printf("CSB: %s MHz\n", strmhz(buf, gd->csb_clk)); 125 126 return 0; 127 } 128 129 int 130 do_reset (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) 131 { 132 ulong msr; 133 #ifndef MPC83xx_RESET 134 ulong addr; 135 #endif 136 137 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; 138 139 puts("Resetting the board.\n"); 140 141 #ifdef MPC83xx_RESET 142 143 /* Interrupts and MMU off */ 144 __asm__ __volatile__ ("mfmsr %0":"=r" (msr):); 145 146 msr &= ~( MSR_EE | MSR_IR | MSR_DR); 147 __asm__ __volatile__ ("mtmsr %0"::"r" (msr)); 148 149 /* enable Reset Control Reg */ 150 immap->reset.rpr = 0x52535445; 151 __asm__ __volatile__ ("sync"); 152 __asm__ __volatile__ ("isync"); 153 154 /* confirm Reset Control Reg is enabled */ 155 while(!((immap->reset.rcer) & RCER_CRE)); 156 157 udelay(200); 158 159 /* perform reset, only one bit */ 160 immap->reset.rcr = RCR_SWHR; 161 162 #else /* ! MPC83xx_RESET */ 163 164 immap->reset.rmr = RMR_CSRE; /* Checkstop Reset enable */ 165 166 /* Interrupts and MMU off */ 167 __asm__ __volatile__ ("mfmsr %0":"=r" (msr):); 168 169 msr &= ~(MSR_ME | MSR_EE | MSR_IR | MSR_DR); 170 __asm__ __volatile__ ("mtmsr %0"::"r" (msr)); 171 172 /* 173 * Trying to execute the next instruction at a non-existing address 174 * should cause a machine check, resulting in reset 175 */ 176 addr = CONFIG_SYS_RESET_ADDRESS; 177 178 ((void (*)(void)) addr) (); 179 #endif /* MPC83xx_RESET */ 180 181 return 1; 182 } 183 184 185 /* 186 * Get timebase clock frequency (like cpu_clk in Hz) 187 */ 188 189 unsigned long get_tbclk(void) 190 { 191 ulong tbclk; 192 193 tbclk = (gd->bus_clk + 3L) / 4L; 194 195 return tbclk; 196 } 197 198 199 #if defined(CONFIG_WATCHDOG) 200 void watchdog_reset (void) 201 { 202 int re_enable = disable_interrupts(); 203 204 /* Reset the 83xx watchdog */ 205 volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; 206 immr->wdt.swsrr = 0x556c; 207 immr->wdt.swsrr = 0xaa39; 208 209 if (re_enable) 210 enable_interrupts (); 211 } 212 #endif 213 214 /* 215 * Initializes on-chip ethernet controllers. 216 * to override, implement board_eth_init() 217 */ 218 int cpu_eth_init(bd_t *bis) 219 { 220 #if defined(CONFIG_UEC_ETH) 221 uec_standard_init(bis); 222 #endif 223 224 #if defined(CONFIG_TSEC_ENET) 225 tsec_standard_init(bis); 226 #endif 227 return 0; 228 } 229 230 /* 231 * Initializes on-chip MMC controllers. 232 * to override, implement board_mmc_init() 233 */ 234 int cpu_mmc_init(bd_t *bis) 235 { 236 #ifdef CONFIG_FSL_ESDHC 237 return fsl_esdhc_mmc_init(bis); 238 #else 239 return 0; 240 #endif 241 } 242