xref: /openbmc/u-boot/arch/powerpc/cpu/mpc83xx/Makefile (revision 02b3bf39)
1#
2# (C) Copyright 2006
3# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4#
5# Copyright 2004 Freescale Semiconductor, Inc.
6#
7# SPDX-License-Identifier:	GPL-2.0+
8#
9
10MINIMAL=
11
12ifdef CONFIG_SPL_BUILD
13ifdef CONFIG_SPL_INIT_MINIMAL
14MINIMAL=y
15endif
16endif
17
18extra-y	= start.o
19
20ifdef MINIMAL
21
22obj-y	+= spl_minimal.o
23
24else
25
26obj-y += traps.o
27obj-y += cpu.o
28obj-y += cpu_init.o
29obj-y += speed.o
30obj-y += interrupts.o
31obj-y += ecc.o
32obj-$(CONFIG_QE) += qe_io.o
33obj-$(CONFIG_FSL_SERDES) += serdes.o
34obj-$(CONFIG_PCI) += pci.o
35obj-$(CONFIG_PCIE) += pcie.o
36obj-$(CONFIG_OF_LIBFDT) += fdt.o
37
38# Stub implementations of cache management functions for USB
39obj-y += cache.o
40
41ifdef CONFIG_FSL_DDR2
42obj-$(CONFIG_MPC8349) += ddr-gen2.o
43SRCS += $(obj)ddr-gen2.c
44else
45obj-y += spd_sdram.o
46endif
47obj-$(CONFIG_FSL_DDR2) += law.o
48
49endif # not minimal
50
51$(obj)ddr-gen1.c:
52	ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/ddr-gen1.c $(obj)ddr-gen1.c
53
54$(obj)ddr-gen2.c:
55	ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/ddr-gen2.c $(obj)ddr-gen2.c
56
57$(obj)ddr-gen3.c:
58	ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/ddr-gen3.c $(obj)ddr-gen3.c
59