xref: /openbmc/u-boot/arch/nios2/include/asm/io.h (revision 83bf0057)
1 /*
2  * (C) Copyright 2004, Psyent Corporation <www.psyent.com>
3  * Scott McNutt <smcnutt@psyent.com>
4  *
5  * SPDX-License-Identifier:	GPL-2.0+
6  */
7 
8 #ifndef __ASM_NIOS2_IO_H_
9 #define __ASM_NIOS2_IO_H_
10 
11 static inline void sync(void)
12 {
13 	__asm__ __volatile__ ("sync" : : : "memory");
14 }
15 
16 /*
17  * Given a physical address and a length, return a virtual address
18  * that can be used to access the memory range with the caching
19  * properties specified by "flags".
20  */
21 #define MAP_NOCACHE	(0)
22 #define MAP_WRCOMBINE	(0)
23 #define MAP_WRBACK	(0)
24 #define MAP_WRTHROUGH	(0)
25 
26 static inline void *
27 map_physmem(phys_addr_t paddr, unsigned long len, unsigned long flags)
28 {
29 	return (void *)paddr;
30 }
31 
32 /*
33  * Take down a mapping set up by map_physmem().
34  */
35 static inline void unmap_physmem(void *vaddr, unsigned long flags)
36 {
37 
38 }
39 
40 static inline phys_addr_t virt_to_phys(void * vaddr)
41 {
42 	DECLARE_GLOBAL_DATA_PTR;
43 	if (gd->arch.has_mmu)
44 		return (phys_addr_t)vaddr & 0x1fffffff;
45 	else
46 		return (phys_addr_t)vaddr & 0x7fffffff;
47 }
48 
49 static inline void *ioremap(unsigned long physaddr, unsigned long size)
50 {
51 	DECLARE_GLOBAL_DATA_PTR;
52 	return (void *)(gd->arch.io_region_base | physaddr);
53 }
54 
55 #define __raw_writeb(v,a)       (*(volatile unsigned char  *)(a) = (v))
56 #define __raw_writew(v,a)       (*(volatile unsigned short *)(a) = (v))
57 #define __raw_writel(v,a)       (*(volatile unsigned int   *)(a) = (v))
58 
59 #define __raw_readb(a)          (*(volatile unsigned char  *)(a))
60 #define __raw_readw(a)          (*(volatile unsigned short *)(a))
61 #define __raw_readl(a)          (*(volatile unsigned int   *)(a))
62 
63 #define readb(addr)\
64 	({unsigned char val;\
65 	 asm volatile( "ldbio %0, 0(%1)" :"=r"(val) : "r" (addr)); val;})
66 #define readw(addr)\
67 	({unsigned short val;\
68 	 asm volatile( "ldhio %0, 0(%1)" :"=r"(val) : "r" (addr)); val;})
69 #define readl(addr)\
70 	({unsigned long val;\
71 	 asm volatile( "ldwio %0, 0(%1)" :"=r"(val) : "r" (addr)); val;})
72 
73 #define writeb(val,addr)\
74 	asm volatile ("stbio %0, 0(%1)" : : "r" (val), "r" (addr))
75 #define writew(val,addr)\
76 	asm volatile ("sthio %0, 0(%1)" : : "r" (val), "r" (addr))
77 #define writel(val,addr)\
78 	asm volatile ("stwio %0, 0(%1)" : : "r" (val), "r" (addr))
79 
80 #define inb(addr)	readb(addr)
81 #define inw(addr)	readw(addr)
82 #define inl(addr)	readl(addr)
83 #define outb(val, addr)	writeb(val,addr)
84 #define outw(val, addr)	writew(val,addr)
85 #define outl(val, addr)	writel(val,addr)
86 
87 static inline void insb (unsigned long port, void *dst, unsigned long count)
88 {
89 	unsigned char *p = dst;
90 	while (count--) *p++ = inb (port);
91 }
92 static inline void insw (unsigned long port, void *dst, unsigned long count)
93 {
94 	unsigned short *p = dst;
95 	while (count--) *p++ = inw (port);
96 }
97 static inline void insl (unsigned long port, void *dst, unsigned long count)
98 {
99 	unsigned long *p = dst;
100 	while (count--) *p++ = inl (port);
101 }
102 
103 static inline void outsb (unsigned long port, const void *src, unsigned long count)
104 {
105 	const unsigned char *p = src;
106 	while (count--) outb (*p++, port);
107 }
108 
109 static inline void outsw (unsigned long port, const void *src, unsigned long count)
110 {
111 	const unsigned short *p = src;
112 	while (count--) outw (*p++, port);
113 }
114 static inline void outsl (unsigned long port, const void *src, unsigned long count)
115 {
116 	const unsigned long *p = src;
117 	while (count--) outl (*p++, port);
118 }
119 
120 /*
121  * Clear and set bits in one shot. These macros can be used to clear and
122  * set multiple bits in a register using a single call. These macros can
123  * also be used to set a multiple-bit bit pattern using a mask, by
124  * specifying the mask in the 'clear' parameter and the new bit pattern
125  * in the 'set' parameter.
126  */
127 
128 #define out_arch(type,endian,a,v)	__raw_write##type(cpu_to_##endian(v),a)
129 #define in_arch(type,endian,a)		endian##_to_cpu(__raw_read##type(a))
130 
131 #define out_le32(a,v)	out_arch(l,le32,a,v)
132 #define out_le16(a,v)	out_arch(w,le16,a,v)
133 
134 #define in_le32(a)	in_arch(l,le32,a)
135 #define in_le16(a)	in_arch(w,le16,a)
136 
137 #define out_be32(a,v)	out_arch(l,be32,a,v)
138 #define out_be16(a,v)	out_arch(w,be16,a,v)
139 
140 #define in_be32(a)	in_arch(l,be32,a)
141 #define in_be16(a)	in_arch(w,be16,a)
142 
143 #define out_8(a,v)	__raw_writeb(v,a)
144 #define in_8(a)		__raw_readb(a)
145 
146 #define clrbits(type, addr, clear) \
147 	out_##type((addr), in_##type(addr) & ~(clear))
148 
149 #define setbits(type, addr, set) \
150 	out_##type((addr), in_##type(addr) | (set))
151 
152 #define clrsetbits(type, addr, clear, set) \
153 	out_##type((addr), (in_##type(addr) & ~(clear)) | (set))
154 
155 #define clrbits_be32(addr, clear) clrbits(be32, addr, clear)
156 #define setbits_be32(addr, set) setbits(be32, addr, set)
157 #define clrsetbits_be32(addr, clear, set) clrsetbits(be32, addr, clear, set)
158 
159 #define clrbits_le32(addr, clear) clrbits(le32, addr, clear)
160 #define setbits_le32(addr, set) setbits(le32, addr, set)
161 #define clrsetbits_le32(addr, clear, set) clrsetbits(le32, addr, clear, set)
162 
163 #define clrbits_be16(addr, clear) clrbits(be16, addr, clear)
164 #define setbits_be16(addr, set) setbits(be16, addr, set)
165 #define clrsetbits_be16(addr, clear, set) clrsetbits(be16, addr, clear, set)
166 
167 #define clrbits_le16(addr, clear) clrbits(le16, addr, clear)
168 #define setbits_le16(addr, set) setbits(le16, addr, set)
169 #define clrsetbits_le16(addr, clear, set) clrsetbits(le16, addr, clear, set)
170 
171 #define clrbits_8(addr, clear) clrbits(8, addr, clear)
172 #define setbits_8(addr, set) setbits(8, addr, set)
173 #define clrsetbits_8(addr, clear, set) clrsetbits(8, addr, clear, set)
174 
175 #endif /* __ASM_NIOS2_IO_H_ */
176