1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */ 2819833afSPeter Tyser /* 3819833afSPeter Tyser * (C) Copyright 2004, Psyent Corporation <www.psyent.com> 4819833afSPeter Tyser * Scott McNutt <smcnutt@psyent.com> 5819833afSPeter Tyser */ 6819833afSPeter Tyser 7819833afSPeter Tyser #ifndef __ASM_NIOS2_CACHE_H_ 8819833afSPeter Tyser #define __ASM_NIOS2_CACHE_H_ 9819833afSPeter Tyser 106fa6035fSAnton Staaf /* 1121ff7344SThomas Chou * Valid L1 data cache line sizes for the NIOS2 architecture are 4, 1221ff7344SThomas Chou * 16, and 32 bytes. We default to the largest of these values for 1321ff7344SThomas Chou * alignment of DMA buffers. 146fa6035fSAnton Staaf */ 156fa6035fSAnton Staaf #define ARCH_DMA_MINALIGN 32 166fa6035fSAnton Staaf 17819833afSPeter Tyser #endif /* __ASM_NIOS2_CACHE_H_ */ 18