1*51c580c6SStefan Roese /* 2*51c580c6SStefan Roese * Copyright (c) 2014, Steffen Trumtrar <s.trumtrar@pengutronix.de> 3*51c580c6SStefan Roese * 4*51c580c6SStefan Roese * This software is licensed under the terms of the GNU General Public 5*51c580c6SStefan Roese * License version 2, as published by the Free Software Foundation, and 6*51c580c6SStefan Roese * may be copied, distributed, and modified under those terms. 7*51c580c6SStefan Roese * 8*51c580c6SStefan Roese * This program is distributed in the hope that it will be useful, 9*51c580c6SStefan Roese * but WITHOUT ANY WARRANTY; without even the implied warranty of 10*51c580c6SStefan Roese * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11*51c580c6SStefan Roese * GNU General Public License for more details. 12*51c580c6SStefan Roese */ 13*51c580c6SStefan Roese 14*51c580c6SStefan Roese #ifndef _DT_BINDINGS_RESET_ALTR_RST_MGR_H 15*51c580c6SStefan Roese #define _DT_BINDINGS_RESET_ALTR_RST_MGR_H 16*51c580c6SStefan Roese 17*51c580c6SStefan Roese /* MPUMODRST */ 18*51c580c6SStefan Roese #define CPU0_RESET 0 19*51c580c6SStefan Roese #define CPU1_RESET 1 20*51c580c6SStefan Roese #define WDS_RESET 2 21*51c580c6SStefan Roese #define SCUPER_RESET 3 22*51c580c6SStefan Roese #define L2_RESET 4 23*51c580c6SStefan Roese 24*51c580c6SStefan Roese /* PERMODRST */ 25*51c580c6SStefan Roese #define EMAC0_RESET 32 26*51c580c6SStefan Roese #define EMAC1_RESET 33 27*51c580c6SStefan Roese #define USB0_RESET 34 28*51c580c6SStefan Roese #define USB1_RESET 35 29*51c580c6SStefan Roese #define NAND_RESET 36 30*51c580c6SStefan Roese #define QSPI_RESET 37 31*51c580c6SStefan Roese #define L4WD0_RESET 38 32*51c580c6SStefan Roese #define L4WD1_RESET 39 33*51c580c6SStefan Roese #define OSC1TIMER0_RESET 40 34*51c580c6SStefan Roese #define OSC1TIMER1_RESET 41 35*51c580c6SStefan Roese #define SPTIMER0_RESET 42 36*51c580c6SStefan Roese #define SPTIMER1_RESET 43 37*51c580c6SStefan Roese #define I2C0_RESET 44 38*51c580c6SStefan Roese #define I2C1_RESET 45 39*51c580c6SStefan Roese #define I2C2_RESET 46 40*51c580c6SStefan Roese #define I2C3_RESET 47 41*51c580c6SStefan Roese #define UART0_RESET 48 42*51c580c6SStefan Roese #define UART1_RESET 49 43*51c580c6SStefan Roese #define SPIM0_RESET 50 44*51c580c6SStefan Roese #define SPIM1_RESET 51 45*51c580c6SStefan Roese #define SPIS0_RESET 52 46*51c580c6SStefan Roese #define SPIS1_RESET 53 47*51c580c6SStefan Roese #define SDMMC_RESET 54 48*51c580c6SStefan Roese #define CAN0_RESET 55 49*51c580c6SStefan Roese #define CAN1_RESET 56 50*51c580c6SStefan Roese #define GPIO0_RESET 57 51*51c580c6SStefan Roese #define GPIO1_RESET 58 52*51c580c6SStefan Roese #define GPIO2_RESET 59 53*51c580c6SStefan Roese #define DMA_RESET 60 54*51c580c6SStefan Roese #define SDR_RESET 61 55*51c580c6SStefan Roese 56*51c580c6SStefan Roese /* PER2MODRST */ 57*51c580c6SStefan Roese #define DMAIF0_RESET 64 58*51c580c6SStefan Roese #define DMAIF1_RESET 65 59*51c580c6SStefan Roese #define DMAIF2_RESET 66 60*51c580c6SStefan Roese #define DMAIF3_RESET 67 61*51c580c6SStefan Roese #define DMAIF4_RESET 68 62*51c580c6SStefan Roese #define DMAIF5_RESET 69 63*51c580c6SStefan Roese #define DMAIF6_RESET 70 64*51c580c6SStefan Roese #define DMAIF7_RESET 71 65*51c580c6SStefan Roese 66*51c580c6SStefan Roese /* BRGMODRST */ 67*51c580c6SStefan Roese #define HPS2FPGA_RESET 96 68*51c580c6SStefan Roese #define LWHPS2FPGA_RESET 97 69*51c580c6SStefan Roese #define FPGA2HPS_RESET 98 70*51c580c6SStefan Roese 71*51c580c6SStefan Roese /* MISCMODRST*/ 72*51c580c6SStefan Roese #define ROM_RESET 128 73*51c580c6SStefan Roese #define OCRAM_RESET 129 74*51c580c6SStefan Roese #define SYSMGR_RESET 130 75*51c580c6SStefan Roese #define SYSMGRCOLD_RESET 131 76*51c580c6SStefan Roese #define FPGAMGR_RESET 132 77*51c580c6SStefan Roese #define ACPIDMAP_RESET 133 78*51c580c6SStefan Roese #define S2F_RESET 134 79*51c580c6SStefan Roese #define S2FCOLD_RESET 135 80*51c580c6SStefan Roese #define NRSTPIN_RESET 136 81*51c580c6SStefan Roese #define TIMESTAMPCOLD_RESET 137 82*51c580c6SStefan Roese #define CLKMGRCOLD_RESET 138 83*51c580c6SStefan Roese #define SCANMGR_RESET 139 84*51c580c6SStefan Roese #define FRZCTRLCOLD_RESET 140 85*51c580c6SStefan Roese #define SYSDBG_RESET 141 86*51c580c6SStefan Roese #define DBG_RESET 142 87*51c580c6SStefan Roese #define TAPCOLD_RESET 143 88*51c580c6SStefan Roese #define SDRCOLD_RESET 144 89*51c580c6SStefan Roese 90*51c580c6SStefan Roese #endif 91