1*797c3c13SMichael Kurz #ifndef _DT_BINDINGS_STM32F746_PINFUNC_H
2*797c3c13SMichael Kurz #define _DT_BINDINGS_STM32F746_PINFUNC_H
3*797c3c13SMichael Kurz 
4*797c3c13SMichael Kurz #define STM32F746_PA0_FUNC_GPIO 0x0
5*797c3c13SMichael Kurz #define STM32F746_PA0_FUNC_TIM2_CH1_TIM2_ETR 0x2
6*797c3c13SMichael Kurz #define STM32F746_PA0_FUNC_TIM5_CH1 0x3
7*797c3c13SMichael Kurz #define STM32F746_PA0_FUNC_TIM8_ETR 0x4
8*797c3c13SMichael Kurz #define STM32F746_PA0_FUNC_USART2_CTS 0x8
9*797c3c13SMichael Kurz #define STM32F746_PA0_FUNC_UART4_TX 0x9
10*797c3c13SMichael Kurz #define STM32F746_PA0_FUNC_SAI2_SD_B 0xb
11*797c3c13SMichael Kurz #define STM32F746_PA0_FUNC_ETH_MII_CRS 0xc
12*797c3c13SMichael Kurz #define STM32F746_PA0_FUNC_EVENTOUT 0x10
13*797c3c13SMichael Kurz #define STM32F746_PA0_FUNC_ANALOG 0x11
14*797c3c13SMichael Kurz 
15*797c3c13SMichael Kurz #define STM32F746_PA1_FUNC_GPIO 0x100
16*797c3c13SMichael Kurz #define STM32F746_PA1_FUNC_TIM2_CH2 0x102
17*797c3c13SMichael Kurz #define STM32F746_PA1_FUNC_TIM5_CH2 0x103
18*797c3c13SMichael Kurz #define STM32F746_PA1_FUNC_USART2_RTS 0x108
19*797c3c13SMichael Kurz #define STM32F746_PA1_FUNC_UART4_RX 0x109
20*797c3c13SMichael Kurz #define STM32F746_PA1_FUNC_QUADSPI_BK1_IO3 0x10a
21*797c3c13SMichael Kurz #define STM32F746_PA1_FUNC_SAI2_MCLK_B 0x10b
22*797c3c13SMichael Kurz #define STM32F746_PA1_FUNC_ETH_MII_RX_CLK_ETH_RMII_REF_CLK 0x10c
23*797c3c13SMichael Kurz #define STM32F746_PA1_FUNC_LCD_R2 0x10f
24*797c3c13SMichael Kurz #define STM32F746_PA1_FUNC_EVENTOUT 0x110
25*797c3c13SMichael Kurz #define STM32F746_PA1_FUNC_ANALOG 0x111
26*797c3c13SMichael Kurz 
27*797c3c13SMichael Kurz #define STM32F746_PA2_FUNC_GPIO 0x200
28*797c3c13SMichael Kurz #define STM32F746_PA2_FUNC_TIM2_CH3 0x202
29*797c3c13SMichael Kurz #define STM32F746_PA2_FUNC_TIM5_CH3 0x203
30*797c3c13SMichael Kurz #define STM32F746_PA2_FUNC_TIM9_CH1 0x204
31*797c3c13SMichael Kurz #define STM32F746_PA2_FUNC_USART2_TX 0x208
32*797c3c13SMichael Kurz #define STM32F746_PA2_FUNC_SAI2_SCK_B 0x209
33*797c3c13SMichael Kurz #define STM32F746_PA2_FUNC_ETH_MDIO 0x20c
34*797c3c13SMichael Kurz #define STM32F746_PA2_FUNC_LCD_R1 0x20f
35*797c3c13SMichael Kurz #define STM32F746_PA2_FUNC_EVENTOUT 0x210
36*797c3c13SMichael Kurz #define STM32F746_PA2_FUNC_ANALOG 0x211
37*797c3c13SMichael Kurz 
38*797c3c13SMichael Kurz #define STM32F746_PA3_FUNC_GPIO 0x300
39*797c3c13SMichael Kurz #define STM32F746_PA3_FUNC_TIM2_CH4 0x302
40*797c3c13SMichael Kurz #define STM32F746_PA3_FUNC_TIM5_CH4 0x303
41*797c3c13SMichael Kurz #define STM32F746_PA3_FUNC_TIM9_CH2 0x304
42*797c3c13SMichael Kurz #define STM32F746_PA3_FUNC_USART2_RX 0x308
43*797c3c13SMichael Kurz #define STM32F746_PA3_FUNC_OTG_HS_ULPI_D0 0x30b
44*797c3c13SMichael Kurz #define STM32F746_PA3_FUNC_ETH_MII_COL 0x30c
45*797c3c13SMichael Kurz #define STM32F746_PA3_FUNC_LCD_B5 0x30f
46*797c3c13SMichael Kurz #define STM32F746_PA3_FUNC_EVENTOUT 0x310
47*797c3c13SMichael Kurz #define STM32F746_PA3_FUNC_ANALOG 0x311
48*797c3c13SMichael Kurz 
49*797c3c13SMichael Kurz #define STM32F746_PA4_FUNC_GPIO 0x400
50*797c3c13SMichael Kurz #define STM32F746_PA4_FUNC_SPI1_NSS_I2S1_WS 0x406
51*797c3c13SMichael Kurz #define STM32F746_PA4_FUNC_SPI3_NSS_I2S3_WS 0x407
52*797c3c13SMichael Kurz #define STM32F746_PA4_FUNC_USART2_CK 0x408
53*797c3c13SMichael Kurz #define STM32F746_PA4_FUNC_OTG_HS_SOF 0x40d
54*797c3c13SMichael Kurz #define STM32F746_PA4_FUNC_DCMI_HSYNC 0x40e
55*797c3c13SMichael Kurz #define STM32F746_PA4_FUNC_LCD_VSYNC 0x40f
56*797c3c13SMichael Kurz #define STM32F746_PA4_FUNC_EVENTOUT 0x410
57*797c3c13SMichael Kurz #define STM32F746_PA4_FUNC_ANALOG 0x411
58*797c3c13SMichael Kurz 
59*797c3c13SMichael Kurz #define STM32F746_PA5_FUNC_GPIO 0x500
60*797c3c13SMichael Kurz #define STM32F746_PA5_FUNC_TIM2_CH1_TIM2_ETR 0x502
61*797c3c13SMichael Kurz #define STM32F746_PA5_FUNC_TIM8_CH1N 0x504
62*797c3c13SMichael Kurz #define STM32F746_PA5_FUNC_SPI1_SCK_I2S1_CK 0x506
63*797c3c13SMichael Kurz #define STM32F746_PA5_FUNC_OTG_HS_ULPI_CK 0x50b
64*797c3c13SMichael Kurz #define STM32F746_PA5_FUNC_LCD_R4 0x50f
65*797c3c13SMichael Kurz #define STM32F746_PA5_FUNC_EVENTOUT 0x510
66*797c3c13SMichael Kurz #define STM32F746_PA5_FUNC_ANALOG 0x511
67*797c3c13SMichael Kurz 
68*797c3c13SMichael Kurz #define STM32F746_PA6_FUNC_GPIO 0x600
69*797c3c13SMichael Kurz #define STM32F746_PA6_FUNC_TIM1_BKIN 0x602
70*797c3c13SMichael Kurz #define STM32F746_PA6_FUNC_TIM3_CH1 0x603
71*797c3c13SMichael Kurz #define STM32F746_PA6_FUNC_TIM8_BKIN 0x604
72*797c3c13SMichael Kurz #define STM32F746_PA6_FUNC_SPI1_MISO 0x606
73*797c3c13SMichael Kurz #define STM32F746_PA6_FUNC_TIM13_CH1 0x60a
74*797c3c13SMichael Kurz #define STM32F746_PA6_FUNC_DCMI_PIXCLK 0x60e
75*797c3c13SMichael Kurz #define STM32F746_PA6_FUNC_LCD_G2 0x60f
76*797c3c13SMichael Kurz #define STM32F746_PA6_FUNC_EVENTOUT 0x610
77*797c3c13SMichael Kurz #define STM32F746_PA6_FUNC_ANALOG 0x611
78*797c3c13SMichael Kurz 
79*797c3c13SMichael Kurz #define STM32F746_PA7_FUNC_GPIO 0x700
80*797c3c13SMichael Kurz #define STM32F746_PA7_FUNC_TIM1_CH1N 0x702
81*797c3c13SMichael Kurz #define STM32F746_PA7_FUNC_TIM3_CH2 0x703
82*797c3c13SMichael Kurz #define STM32F746_PA7_FUNC_TIM8_CH1N 0x704
83*797c3c13SMichael Kurz #define STM32F746_PA7_FUNC_SPI1_MOSI_I2S1_SD 0x706
84*797c3c13SMichael Kurz #define STM32F746_PA7_FUNC_TIM14_CH1 0x70a
85*797c3c13SMichael Kurz #define STM32F746_PA7_FUNC_ETH_MII_RX_DV_ETH_RMII_CRS_DV 0x70c
86*797c3c13SMichael Kurz #define STM32F746_PA7_FUNC_FMC_SDNWE 0x70d
87*797c3c13SMichael Kurz #define STM32F746_PA7_FUNC_EVENTOUT 0x710
88*797c3c13SMichael Kurz #define STM32F746_PA7_FUNC_ANALOG 0x711
89*797c3c13SMichael Kurz 
90*797c3c13SMichael Kurz #define STM32F746_PA8_FUNC_GPIO 0x800
91*797c3c13SMichael Kurz #define STM32F746_PA8_FUNC_MCO1 0x801
92*797c3c13SMichael Kurz #define STM32F746_PA8_FUNC_TIM1_CH1 0x802
93*797c3c13SMichael Kurz #define STM32F746_PA8_FUNC_TIM8_BKIN2 0x804
94*797c3c13SMichael Kurz #define STM32F746_PA8_FUNC_I2C3_SCL 0x805
95*797c3c13SMichael Kurz #define STM32F746_PA8_FUNC_USART1_CK 0x808
96*797c3c13SMichael Kurz #define STM32F746_PA8_FUNC_OTG_FS_SOF 0x80b
97*797c3c13SMichael Kurz #define STM32F746_PA8_FUNC_LCD_R6 0x80f
98*797c3c13SMichael Kurz #define STM32F746_PA8_FUNC_EVENTOUT 0x810
99*797c3c13SMichael Kurz #define STM32F746_PA8_FUNC_ANALOG 0x811
100*797c3c13SMichael Kurz 
101*797c3c13SMichael Kurz #define STM32F746_PA9_FUNC_GPIO 0x900
102*797c3c13SMichael Kurz #define STM32F746_PA9_FUNC_TIM1_CH2 0x902
103*797c3c13SMichael Kurz #define STM32F746_PA9_FUNC_I2C3_SMBA 0x905
104*797c3c13SMichael Kurz #define STM32F746_PA9_FUNC_SPI2_SCK_I2S2_CK 0x906
105*797c3c13SMichael Kurz #define STM32F746_PA9_FUNC_USART1_TX 0x908
106*797c3c13SMichael Kurz #define STM32F746_PA9_FUNC_DCMI_D0 0x90e
107*797c3c13SMichael Kurz #define STM32F746_PA9_FUNC_EVENTOUT 0x910
108*797c3c13SMichael Kurz #define STM32F746_PA9_FUNC_ANALOG 0x911
109*797c3c13SMichael Kurz 
110*797c3c13SMichael Kurz #define STM32F746_PA10_FUNC_GPIO 0xa00
111*797c3c13SMichael Kurz #define STM32F746_PA10_FUNC_TIM1_CH3 0xa02
112*797c3c13SMichael Kurz #define STM32F746_PA10_FUNC_USART1_RX 0xa08
113*797c3c13SMichael Kurz #define STM32F746_PA10_FUNC_OTG_FS_ID 0xa0b
114*797c3c13SMichael Kurz #define STM32F746_PA10_FUNC_DCMI_D1 0xa0e
115*797c3c13SMichael Kurz #define STM32F746_PA10_FUNC_EVENTOUT 0xa10
116*797c3c13SMichael Kurz #define STM32F746_PA10_FUNC_ANALOG 0xa11
117*797c3c13SMichael Kurz 
118*797c3c13SMichael Kurz #define STM32F746_PA11_FUNC_GPIO 0xb00
119*797c3c13SMichael Kurz #define STM32F746_PA11_FUNC_TIM1_CH4 0xb02
120*797c3c13SMichael Kurz #define STM32F746_PA11_FUNC_USART1_CTS 0xb08
121*797c3c13SMichael Kurz #define STM32F746_PA11_FUNC_CAN1_RX 0xb0a
122*797c3c13SMichael Kurz #define STM32F746_PA11_FUNC_OTG_FS_DM 0xb0b
123*797c3c13SMichael Kurz #define STM32F746_PA11_FUNC_LCD_R4 0xb0f
124*797c3c13SMichael Kurz #define STM32F746_PA11_FUNC_EVENTOUT 0xb10
125*797c3c13SMichael Kurz #define STM32F746_PA11_FUNC_ANALOG 0xb11
126*797c3c13SMichael Kurz 
127*797c3c13SMichael Kurz #define STM32F746_PA12_FUNC_GPIO 0xc00
128*797c3c13SMichael Kurz #define STM32F746_PA12_FUNC_TIM1_ETR 0xc02
129*797c3c13SMichael Kurz #define STM32F746_PA12_FUNC_USART1_RTS 0xc08
130*797c3c13SMichael Kurz #define STM32F746_PA12_FUNC_SAI2_FS_B 0xc09
131*797c3c13SMichael Kurz #define STM32F746_PA12_FUNC_CAN1_TX 0xc0a
132*797c3c13SMichael Kurz #define STM32F746_PA12_FUNC_OTG_FS_DP 0xc0b
133*797c3c13SMichael Kurz #define STM32F746_PA12_FUNC_LCD_R5 0xc0f
134*797c3c13SMichael Kurz #define STM32F746_PA12_FUNC_EVENTOUT 0xc10
135*797c3c13SMichael Kurz #define STM32F746_PA12_FUNC_ANALOG 0xc11
136*797c3c13SMichael Kurz 
137*797c3c13SMichael Kurz #define STM32F746_PA13_FUNC_GPIO 0xd00
138*797c3c13SMichael Kurz #define STM32F746_PA13_FUNC_JTMS_SWDIO 0xd01
139*797c3c13SMichael Kurz #define STM32F746_PA13_FUNC_EVENTOUT 0xd10
140*797c3c13SMichael Kurz #define STM32F746_PA13_FUNC_ANALOG 0xd11
141*797c3c13SMichael Kurz 
142*797c3c13SMichael Kurz #define STM32F746_PA14_FUNC_GPIO 0xe00
143*797c3c13SMichael Kurz #define STM32F746_PA14_FUNC_JTCK_SWCLK 0xe01
144*797c3c13SMichael Kurz #define STM32F746_PA14_FUNC_EVENTOUT 0xe10
145*797c3c13SMichael Kurz #define STM32F746_PA14_FUNC_ANALOG 0xe11
146*797c3c13SMichael Kurz 
147*797c3c13SMichael Kurz #define STM32F746_PA15_FUNC_GPIO 0xf00
148*797c3c13SMichael Kurz #define STM32F746_PA15_FUNC_JTDI 0xf01
149*797c3c13SMichael Kurz #define STM32F746_PA15_FUNC_TIM2_CH1_TIM2_ETR 0xf02
150*797c3c13SMichael Kurz #define STM32F746_PA15_FUNC_HDMI_CEC 0xf05
151*797c3c13SMichael Kurz #define STM32F746_PA15_FUNC_SPI1_NSS_I2S1_WS 0xf06
152*797c3c13SMichael Kurz #define STM32F746_PA15_FUNC_SPI3_NSS_I2S3_WS 0xf07
153*797c3c13SMichael Kurz #define STM32F746_PA15_FUNC_UART4_RTS 0xf09
154*797c3c13SMichael Kurz #define STM32F746_PA15_FUNC_EVENTOUT 0xf10
155*797c3c13SMichael Kurz #define STM32F746_PA15_FUNC_ANALOG 0xf11
156*797c3c13SMichael Kurz 
157*797c3c13SMichael Kurz 
158*797c3c13SMichael Kurz #define STM32F746_PB0_FUNC_GPIO 0x1000
159*797c3c13SMichael Kurz #define STM32F746_PB0_FUNC_TIM1_CH2N 0x1002
160*797c3c13SMichael Kurz #define STM32F746_PB0_FUNC_TIM3_CH3 0x1003
161*797c3c13SMichael Kurz #define STM32F746_PB0_FUNC_TIM8_CH2N 0x1004
162*797c3c13SMichael Kurz #define STM32F746_PB0_FUNC_UART4_CTS 0x1009
163*797c3c13SMichael Kurz #define STM32F746_PB0_FUNC_LCD_R3 0x100a
164*797c3c13SMichael Kurz #define STM32F746_PB0_FUNC_OTG_HS_ULPI_D1 0x100b
165*797c3c13SMichael Kurz #define STM32F746_PB0_FUNC_ETH_MII_RXD2 0x100c
166*797c3c13SMichael Kurz #define STM32F746_PB0_FUNC_EVENTOUT 0x1010
167*797c3c13SMichael Kurz #define STM32F746_PB0_FUNC_ANALOG 0x1011
168*797c3c13SMichael Kurz 
169*797c3c13SMichael Kurz #define STM32F746_PB1_FUNC_GPIO 0x1100
170*797c3c13SMichael Kurz #define STM32F746_PB1_FUNC_TIM1_CH3N 0x1102
171*797c3c13SMichael Kurz #define STM32F746_PB1_FUNC_TIM3_CH4 0x1103
172*797c3c13SMichael Kurz #define STM32F746_PB1_FUNC_TIM8_CH3N 0x1104
173*797c3c13SMichael Kurz #define STM32F746_PB1_FUNC_LCD_R6 0x110a
174*797c3c13SMichael Kurz #define STM32F746_PB1_FUNC_OTG_HS_ULPI_D2 0x110b
175*797c3c13SMichael Kurz #define STM32F746_PB1_FUNC_ETH_MII_RXD3 0x110c
176*797c3c13SMichael Kurz #define STM32F746_PB1_FUNC_EVENTOUT 0x1110
177*797c3c13SMichael Kurz #define STM32F746_PB1_FUNC_ANALOG 0x1111
178*797c3c13SMichael Kurz 
179*797c3c13SMichael Kurz #define STM32F746_PB2_FUNC_GPIO 0x1200
180*797c3c13SMichael Kurz #define STM32F746_PB2_FUNC_SAI1_SD_A 0x1207
181*797c3c13SMichael Kurz #define STM32F746_PB2_FUNC_SPI3_MOSI_I2S3_SD 0x1208
182*797c3c13SMichael Kurz #define STM32F746_PB2_FUNC_QUADSPI_CLK 0x120a
183*797c3c13SMichael Kurz #define STM32F746_PB2_FUNC_EVENTOUT 0x1210
184*797c3c13SMichael Kurz #define STM32F746_PB2_FUNC_ANALOG 0x1211
185*797c3c13SMichael Kurz 
186*797c3c13SMichael Kurz #define STM32F746_PB3_FUNC_GPIO 0x1300
187*797c3c13SMichael Kurz #define STM32F746_PB3_FUNC_JTDO_TRACESWO 0x1301
188*797c3c13SMichael Kurz #define STM32F746_PB3_FUNC_TIM2_CH2 0x1302
189*797c3c13SMichael Kurz #define STM32F746_PB3_FUNC_SPI1_SCK_I2S1_CK 0x1306
190*797c3c13SMichael Kurz #define STM32F746_PB3_FUNC_SPI3_SCK_I2S3_CK 0x1307
191*797c3c13SMichael Kurz #define STM32F746_PB3_FUNC_EVENTOUT 0x1310
192*797c3c13SMichael Kurz #define STM32F746_PB3_FUNC_ANALOG 0x1311
193*797c3c13SMichael Kurz 
194*797c3c13SMichael Kurz #define STM32F746_PB4_FUNC_GPIO 0x1400
195*797c3c13SMichael Kurz #define STM32F746_PB4_FUNC_NJTRST 0x1401
196*797c3c13SMichael Kurz #define STM32F746_PB4_FUNC_TIM3_CH1 0x1403
197*797c3c13SMichael Kurz #define STM32F746_PB4_FUNC_SPI1_MISO 0x1406
198*797c3c13SMichael Kurz #define STM32F746_PB4_FUNC_SPI3_MISO 0x1407
199*797c3c13SMichael Kurz #define STM32F746_PB4_FUNC_SPI2_NSS_I2S2_WS 0x1408
200*797c3c13SMichael Kurz #define STM32F746_PB4_FUNC_EVENTOUT 0x1410
201*797c3c13SMichael Kurz #define STM32F746_PB4_FUNC_ANALOG 0x1411
202*797c3c13SMichael Kurz 
203*797c3c13SMichael Kurz #define STM32F746_PB5_FUNC_GPIO 0x1500
204*797c3c13SMichael Kurz #define STM32F746_PB5_FUNC_TIM3_CH2 0x1503
205*797c3c13SMichael Kurz #define STM32F746_PB5_FUNC_I2C1_SMBA 0x1505
206*797c3c13SMichael Kurz #define STM32F746_PB5_FUNC_SPI1_MOSI_I2S1_SD 0x1506
207*797c3c13SMichael Kurz #define STM32F746_PB5_FUNC_SPI3_MOSI_I2S3_SD 0x1507
208*797c3c13SMichael Kurz #define STM32F746_PB5_FUNC_CAN2_RX 0x150a
209*797c3c13SMichael Kurz #define STM32F746_PB5_FUNC_OTG_HS_ULPI_D7 0x150b
210*797c3c13SMichael Kurz #define STM32F746_PB5_FUNC_ETH_PPS_OUT 0x150c
211*797c3c13SMichael Kurz #define STM32F746_PB5_FUNC_FMC_SDCKE1 0x150d
212*797c3c13SMichael Kurz #define STM32F746_PB5_FUNC_DCMI_D10 0x150e
213*797c3c13SMichael Kurz #define STM32F746_PB5_FUNC_EVENTOUT 0x1510
214*797c3c13SMichael Kurz #define STM32F746_PB5_FUNC_ANALOG 0x1511
215*797c3c13SMichael Kurz 
216*797c3c13SMichael Kurz #define STM32F746_PB6_FUNC_GPIO 0x1600
217*797c3c13SMichael Kurz #define STM32F746_PB6_FUNC_TIM4_CH1 0x1603
218*797c3c13SMichael Kurz #define STM32F746_PB6_FUNC_HDMI_CEC 0x1604
219*797c3c13SMichael Kurz #define STM32F746_PB6_FUNC_I2C1_SCL 0x1605
220*797c3c13SMichael Kurz #define STM32F746_PB6_FUNC_USART1_TX 0x1608
221*797c3c13SMichael Kurz #define STM32F746_PB6_FUNC_CAN2_TX 0x160a
222*797c3c13SMichael Kurz #define STM32F746_PB6_FUNC_QUADSPI_BK1_NCS 0x160b
223*797c3c13SMichael Kurz #define STM32F746_PB6_FUNC_FMC_SDNE1 0x160d
224*797c3c13SMichael Kurz #define STM32F746_PB6_FUNC_DCMI_D5 0x160e
225*797c3c13SMichael Kurz #define STM32F746_PB6_FUNC_EVENTOUT 0x1610
226*797c3c13SMichael Kurz #define STM32F746_PB6_FUNC_ANALOG 0x1611
227*797c3c13SMichael Kurz 
228*797c3c13SMichael Kurz #define STM32F746_PB7_FUNC_GPIO 0x1700
229*797c3c13SMichael Kurz #define STM32F746_PB7_FUNC_TIM4_CH2 0x1703
230*797c3c13SMichael Kurz #define STM32F746_PB7_FUNC_I2C1_SDA 0x1705
231*797c3c13SMichael Kurz #define STM32F746_PB7_FUNC_USART1_RX 0x1708
232*797c3c13SMichael Kurz #define STM32F746_PB7_FUNC_FMC_NL 0x170d
233*797c3c13SMichael Kurz #define STM32F746_PB7_FUNC_DCMI_VSYNC 0x170e
234*797c3c13SMichael Kurz #define STM32F746_PB7_FUNC_EVENTOUT 0x1710
235*797c3c13SMichael Kurz #define STM32F746_PB7_FUNC_ANALOG 0x1711
236*797c3c13SMichael Kurz 
237*797c3c13SMichael Kurz #define STM32F746_PB8_FUNC_GPIO 0x1800
238*797c3c13SMichael Kurz #define STM32F746_PB8_FUNC_TIM4_CH3 0x1803
239*797c3c13SMichael Kurz #define STM32F746_PB8_FUNC_TIM10_CH1 0x1804
240*797c3c13SMichael Kurz #define STM32F746_PB8_FUNC_I2C1_SCL 0x1805
241*797c3c13SMichael Kurz #define STM32F746_PB8_FUNC_CAN1_RX 0x180a
242*797c3c13SMichael Kurz #define STM32F746_PB8_FUNC_ETH_MII_TXD3 0x180c
243*797c3c13SMichael Kurz #define STM32F746_PB8_FUNC_SDMMC1_D4 0x180d
244*797c3c13SMichael Kurz #define STM32F746_PB8_FUNC_DCMI_D6 0x180e
245*797c3c13SMichael Kurz #define STM32F746_PB8_FUNC_LCD_B6 0x180f
246*797c3c13SMichael Kurz #define STM32F746_PB8_FUNC_EVENTOUT 0x1810
247*797c3c13SMichael Kurz #define STM32F746_PB8_FUNC_ANALOG 0x1811
248*797c3c13SMichael Kurz 
249*797c3c13SMichael Kurz #define STM32F746_PB9_FUNC_GPIO 0x1900
250*797c3c13SMichael Kurz #define STM32F746_PB9_FUNC_TIM4_CH4 0x1903
251*797c3c13SMichael Kurz #define STM32F746_PB9_FUNC_TIM11_CH1 0x1904
252*797c3c13SMichael Kurz #define STM32F746_PB9_FUNC_I2C1_SDA 0x1905
253*797c3c13SMichael Kurz #define STM32F746_PB9_FUNC_SPI2_NSS_I2S2_WS 0x1906
254*797c3c13SMichael Kurz #define STM32F746_PB9_FUNC_CAN1_TX 0x190a
255*797c3c13SMichael Kurz #define STM32F746_PB9_FUNC_SDMMC1_D5 0x190d
256*797c3c13SMichael Kurz #define STM32F746_PB9_FUNC_DCMI_D7 0x190e
257*797c3c13SMichael Kurz #define STM32F746_PB9_FUNC_LCD_B7 0x190f
258*797c3c13SMichael Kurz #define STM32F746_PB9_FUNC_EVENTOUT 0x1910
259*797c3c13SMichael Kurz #define STM32F746_PB9_FUNC_ANALOG 0x1911
260*797c3c13SMichael Kurz 
261*797c3c13SMichael Kurz #define STM32F746_PB10_FUNC_GPIO 0x1a00
262*797c3c13SMichael Kurz #define STM32F746_PB10_FUNC_TIM2_CH3 0x1a02
263*797c3c13SMichael Kurz #define STM32F746_PB10_FUNC_I2C2_SCL 0x1a05
264*797c3c13SMichael Kurz #define STM32F746_PB10_FUNC_SPI2_SCK_I2S2_CK 0x1a06
265*797c3c13SMichael Kurz #define STM32F746_PB10_FUNC_USART3_TX 0x1a08
266*797c3c13SMichael Kurz #define STM32F746_PB10_FUNC_OTG_HS_ULPI_D3 0x1a0b
267*797c3c13SMichael Kurz #define STM32F746_PB10_FUNC_ETH_MII_RX_ER 0x1a0c
268*797c3c13SMichael Kurz #define STM32F746_PB10_FUNC_LCD_G4 0x1a0f
269*797c3c13SMichael Kurz #define STM32F746_PB10_FUNC_EVENTOUT 0x1a10
270*797c3c13SMichael Kurz #define STM32F746_PB10_FUNC_ANALOG 0x1a11
271*797c3c13SMichael Kurz 
272*797c3c13SMichael Kurz #define STM32F746_PB11_FUNC_GPIO 0x1b00
273*797c3c13SMichael Kurz #define STM32F746_PB11_FUNC_TIM2_CH4 0x1b02
274*797c3c13SMichael Kurz #define STM32F746_PB11_FUNC_I2C2_SDA 0x1b05
275*797c3c13SMichael Kurz #define STM32F746_PB11_FUNC_USART3_RX 0x1b08
276*797c3c13SMichael Kurz #define STM32F746_PB11_FUNC_OTG_HS_ULPI_D4 0x1b0b
277*797c3c13SMichael Kurz #define STM32F746_PB11_FUNC_ETH_MII_TX_EN_ETH_RMII_TX_EN 0x1b0c
278*797c3c13SMichael Kurz #define STM32F746_PB11_FUNC_LCD_G5 0x1b0f
279*797c3c13SMichael Kurz #define STM32F746_PB11_FUNC_EVENTOUT 0x1b10
280*797c3c13SMichael Kurz #define STM32F746_PB11_FUNC_ANALOG 0x1b11
281*797c3c13SMichael Kurz 
282*797c3c13SMichael Kurz #define STM32F746_PB12_FUNC_GPIO 0x1c00
283*797c3c13SMichael Kurz #define STM32F746_PB12_FUNC_TIM1_BKIN 0x1c02
284*797c3c13SMichael Kurz #define STM32F746_PB12_FUNC_I2C2_SMBA 0x1c05
285*797c3c13SMichael Kurz #define STM32F746_PB12_FUNC_SPI2_NSS_I2S2_WS 0x1c06
286*797c3c13SMichael Kurz #define STM32F746_PB12_FUNC_USART3_CK 0x1c08
287*797c3c13SMichael Kurz #define STM32F746_PB12_FUNC_CAN2_RX 0x1c0a
288*797c3c13SMichael Kurz #define STM32F746_PB12_FUNC_OTG_HS_ULPI_D5 0x1c0b
289*797c3c13SMichael Kurz #define STM32F746_PB12_FUNC_ETH_MII_TXD0_ETH_RMII_TXD0 0x1c0c
290*797c3c13SMichael Kurz #define STM32F746_PB12_FUNC_OTG_HS_ID 0x1c0d
291*797c3c13SMichael Kurz #define STM32F746_PB12_FUNC_EVENTOUT 0x1c10
292*797c3c13SMichael Kurz #define STM32F746_PB12_FUNC_ANALOG 0x1c11
293*797c3c13SMichael Kurz 
294*797c3c13SMichael Kurz #define STM32F746_PB13_FUNC_GPIO 0x1d00
295*797c3c13SMichael Kurz #define STM32F746_PB13_FUNC_TIM1_CH1N 0x1d02
296*797c3c13SMichael Kurz #define STM32F746_PB13_FUNC_SPI2_SCK_I2S2_CK 0x1d06
297*797c3c13SMichael Kurz #define STM32F746_PB13_FUNC_USART3_CTS 0x1d08
298*797c3c13SMichael Kurz #define STM32F746_PB13_FUNC_CAN2_TX 0x1d0a
299*797c3c13SMichael Kurz #define STM32F746_PB13_FUNC_OTG_HS_ULPI_D6 0x1d0b
300*797c3c13SMichael Kurz #define STM32F746_PB13_FUNC_ETH_MII_TXD1_ETH_RMII_TXD1 0x1d0c
301*797c3c13SMichael Kurz #define STM32F746_PB13_FUNC_EVENTOUT 0x1d10
302*797c3c13SMichael Kurz #define STM32F746_PB13_FUNC_ANALOG 0x1d11
303*797c3c13SMichael Kurz 
304*797c3c13SMichael Kurz #define STM32F746_PB14_FUNC_GPIO 0x1e00
305*797c3c13SMichael Kurz #define STM32F746_PB14_FUNC_TIM1_CH2N 0x1e02
306*797c3c13SMichael Kurz #define STM32F746_PB14_FUNC_TIM8_CH2N 0x1e04
307*797c3c13SMichael Kurz #define STM32F746_PB14_FUNC_SPI2_MISO 0x1e06
308*797c3c13SMichael Kurz #define STM32F746_PB14_FUNC_USART3_RTS 0x1e08
309*797c3c13SMichael Kurz #define STM32F746_PB14_FUNC_TIM12_CH1 0x1e0a
310*797c3c13SMichael Kurz #define STM32F746_PB14_FUNC_OTG_HS_DM 0x1e0d
311*797c3c13SMichael Kurz #define STM32F746_PB14_FUNC_EVENTOUT 0x1e10
312*797c3c13SMichael Kurz #define STM32F746_PB14_FUNC_ANALOG 0x1e11
313*797c3c13SMichael Kurz 
314*797c3c13SMichael Kurz #define STM32F746_PB15_FUNC_GPIO 0x1f00
315*797c3c13SMichael Kurz #define STM32F746_PB15_FUNC_RTC_REFIN 0x1f01
316*797c3c13SMichael Kurz #define STM32F746_PB15_FUNC_TIM1_CH3N 0x1f02
317*797c3c13SMichael Kurz #define STM32F746_PB15_FUNC_TIM8_CH3N 0x1f04
318*797c3c13SMichael Kurz #define STM32F746_PB15_FUNC_SPI2_MOSI_I2S2_SD 0x1f06
319*797c3c13SMichael Kurz #define STM32F746_PB15_FUNC_TIM12_CH2 0x1f0a
320*797c3c13SMichael Kurz #define STM32F746_PB15_FUNC_OTG_HS_DP 0x1f0d
321*797c3c13SMichael Kurz #define STM32F746_PB15_FUNC_EVENTOUT 0x1f10
322*797c3c13SMichael Kurz #define STM32F746_PB15_FUNC_ANALOG 0x1f11
323*797c3c13SMichael Kurz 
324*797c3c13SMichael Kurz 
325*797c3c13SMichael Kurz #define STM32F746_PC0_FUNC_GPIO 0x2000
326*797c3c13SMichael Kurz #define STM32F746_PC0_FUNC_SAI2_FS_B 0x2009
327*797c3c13SMichael Kurz #define STM32F746_PC0_FUNC_OTG_HS_ULPI_STP 0x200b
328*797c3c13SMichael Kurz #define STM32F746_PC0_FUNC_FMC_SDNWE 0x200d
329*797c3c13SMichael Kurz #define STM32F746_PC0_FUNC_LCD_R5 0x200f
330*797c3c13SMichael Kurz #define STM32F746_PC0_FUNC_EVENTOUT 0x2010
331*797c3c13SMichael Kurz #define STM32F746_PC0_FUNC_ANALOG 0x2011
332*797c3c13SMichael Kurz 
333*797c3c13SMichael Kurz #define STM32F746_PC1_FUNC_GPIO 0x2100
334*797c3c13SMichael Kurz #define STM32F746_PC1_FUNC_TRACED0 0x2101
335*797c3c13SMichael Kurz #define STM32F746_PC1_FUNC_SPI2_MOSI_I2S2_SD 0x2106
336*797c3c13SMichael Kurz #define STM32F746_PC1_FUNC_SAI1_SD_A 0x2107
337*797c3c13SMichael Kurz #define STM32F746_PC1_FUNC_ETH_MDC 0x210c
338*797c3c13SMichael Kurz #define STM32F746_PC1_FUNC_EVENTOUT 0x2110
339*797c3c13SMichael Kurz #define STM32F746_PC1_FUNC_ANALOG 0x2111
340*797c3c13SMichael Kurz 
341*797c3c13SMichael Kurz #define STM32F746_PC2_FUNC_GPIO 0x2200
342*797c3c13SMichael Kurz #define STM32F746_PC2_FUNC_SPI2_MISO 0x2206
343*797c3c13SMichael Kurz #define STM32F746_PC2_FUNC_OTG_HS_ULPI_DIR 0x220b
344*797c3c13SMichael Kurz #define STM32F746_PC2_FUNC_ETH_MII_TXD2 0x220c
345*797c3c13SMichael Kurz #define STM32F746_PC2_FUNC_FMC_SDNE0 0x220d
346*797c3c13SMichael Kurz #define STM32F746_PC2_FUNC_EVENTOUT 0x2210
347*797c3c13SMichael Kurz #define STM32F746_PC2_FUNC_ANALOG 0x2211
348*797c3c13SMichael Kurz 
349*797c3c13SMichael Kurz #define STM32F746_PC3_FUNC_GPIO 0x2300
350*797c3c13SMichael Kurz #define STM32F746_PC3_FUNC_SPI2_MOSI_I2S2_SD 0x2306
351*797c3c13SMichael Kurz #define STM32F746_PC3_FUNC_OTG_HS_ULPI_NXT 0x230b
352*797c3c13SMichael Kurz #define STM32F746_PC3_FUNC_ETH_MII_TX_CLK 0x230c
353*797c3c13SMichael Kurz #define STM32F746_PC3_FUNC_FMC_SDCKE0 0x230d
354*797c3c13SMichael Kurz #define STM32F746_PC3_FUNC_EVENTOUT 0x2310
355*797c3c13SMichael Kurz #define STM32F746_PC3_FUNC_ANALOG 0x2311
356*797c3c13SMichael Kurz 
357*797c3c13SMichael Kurz #define STM32F746_PC4_FUNC_GPIO 0x2400
358*797c3c13SMichael Kurz #define STM32F746_PC4_FUNC_I2S1_MCK 0x2406
359*797c3c13SMichael Kurz #define STM32F746_PC4_FUNC_SPDIFRX_IN2 0x2409
360*797c3c13SMichael Kurz #define STM32F746_PC4_FUNC_ETH_MII_RXD0_ETH_RMII_RXD0 0x240c
361*797c3c13SMichael Kurz #define STM32F746_PC4_FUNC_FMC_SDNE0 0x240d
362*797c3c13SMichael Kurz #define STM32F746_PC4_FUNC_EVENTOUT 0x2410
363*797c3c13SMichael Kurz #define STM32F746_PC4_FUNC_ANALOG 0x2411
364*797c3c13SMichael Kurz 
365*797c3c13SMichael Kurz #define STM32F746_PC5_FUNC_GPIO 0x2500
366*797c3c13SMichael Kurz #define STM32F746_PC5_FUNC_SPDIFRX_IN3 0x2509
367*797c3c13SMichael Kurz #define STM32F746_PC5_FUNC_ETH_MII_RXD1_ETH_RMII_RXD1 0x250c
368*797c3c13SMichael Kurz #define STM32F746_PC5_FUNC_FMC_SDCKE0 0x250d
369*797c3c13SMichael Kurz #define STM32F746_PC5_FUNC_EVENTOUT 0x2510
370*797c3c13SMichael Kurz #define STM32F746_PC5_FUNC_ANALOG 0x2511
371*797c3c13SMichael Kurz 
372*797c3c13SMichael Kurz #define STM32F746_PC6_FUNC_GPIO 0x2600
373*797c3c13SMichael Kurz #define STM32F746_PC6_FUNC_TIM3_CH1 0x2603
374*797c3c13SMichael Kurz #define STM32F746_PC6_FUNC_TIM8_CH1 0x2604
375*797c3c13SMichael Kurz #define STM32F746_PC6_FUNC_I2S2_MCK 0x2606
376*797c3c13SMichael Kurz #define STM32F746_PC6_FUNC_USART6_TX 0x2609
377*797c3c13SMichael Kurz #define STM32F746_PC6_FUNC_SDMMC1_D6 0x260d
378*797c3c13SMichael Kurz #define STM32F746_PC6_FUNC_DCMI_D0 0x260e
379*797c3c13SMichael Kurz #define STM32F746_PC6_FUNC_LCD_HSYNC 0x260f
380*797c3c13SMichael Kurz #define STM32F746_PC6_FUNC_EVENTOUT 0x2610
381*797c3c13SMichael Kurz #define STM32F746_PC6_FUNC_ANALOG 0x2611
382*797c3c13SMichael Kurz 
383*797c3c13SMichael Kurz #define STM32F746_PC7_FUNC_GPIO 0x2700
384*797c3c13SMichael Kurz #define STM32F746_PC7_FUNC_TIM3_CH2 0x2703
385*797c3c13SMichael Kurz #define STM32F746_PC7_FUNC_TIM8_CH2 0x2704
386*797c3c13SMichael Kurz #define STM32F746_PC7_FUNC_I2S3_MCK 0x2707
387*797c3c13SMichael Kurz #define STM32F746_PC7_FUNC_USART6_RX 0x2709
388*797c3c13SMichael Kurz #define STM32F746_PC7_FUNC_SDMMC1_D7 0x270d
389*797c3c13SMichael Kurz #define STM32F746_PC7_FUNC_DCMI_D1 0x270e
390*797c3c13SMichael Kurz #define STM32F746_PC7_FUNC_LCD_G6 0x270f
391*797c3c13SMichael Kurz #define STM32F746_PC7_FUNC_EVENTOUT 0x2710
392*797c3c13SMichael Kurz #define STM32F746_PC7_FUNC_ANALOG 0x2711
393*797c3c13SMichael Kurz 
394*797c3c13SMichael Kurz #define STM32F746_PC8_FUNC_GPIO 0x2800
395*797c3c13SMichael Kurz #define STM32F746_PC8_FUNC_TRACED1 0x2801
396*797c3c13SMichael Kurz #define STM32F746_PC8_FUNC_TIM3_CH3 0x2803
397*797c3c13SMichael Kurz #define STM32F746_PC8_FUNC_TIM8_CH3 0x2804
398*797c3c13SMichael Kurz #define STM32F746_PC8_FUNC_UART5_RTS 0x2808
399*797c3c13SMichael Kurz #define STM32F746_PC8_FUNC_USART6_CK 0x2809
400*797c3c13SMichael Kurz #define STM32F746_PC8_FUNC_SDMMC1_D0 0x280d
401*797c3c13SMichael Kurz #define STM32F746_PC8_FUNC_DCMI_D2 0x280e
402*797c3c13SMichael Kurz #define STM32F746_PC8_FUNC_EVENTOUT 0x2810
403*797c3c13SMichael Kurz #define STM32F746_PC8_FUNC_ANALOG 0x2811
404*797c3c13SMichael Kurz 
405*797c3c13SMichael Kurz #define STM32F746_PC9_FUNC_GPIO 0x2900
406*797c3c13SMichael Kurz #define STM32F746_PC9_FUNC_MCO2 0x2901
407*797c3c13SMichael Kurz #define STM32F746_PC9_FUNC_TIM3_CH4 0x2903
408*797c3c13SMichael Kurz #define STM32F746_PC9_FUNC_TIM8_CH4 0x2904
409*797c3c13SMichael Kurz #define STM32F746_PC9_FUNC_I2C3_SDA 0x2905
410*797c3c13SMichael Kurz #define STM32F746_PC9_FUNC_I2S_CKIN 0x2906
411*797c3c13SMichael Kurz #define STM32F746_PC9_FUNC_UART5_CTS 0x2908
412*797c3c13SMichael Kurz #define STM32F746_PC9_FUNC_QUADSPI_BK1_IO0 0x290a
413*797c3c13SMichael Kurz #define STM32F746_PC9_FUNC_SDMMC1_D1 0x290d
414*797c3c13SMichael Kurz #define STM32F746_PC9_FUNC_DCMI_D3 0x290e
415*797c3c13SMichael Kurz #define STM32F746_PC9_FUNC_EVENTOUT 0x2910
416*797c3c13SMichael Kurz #define STM32F746_PC9_FUNC_ANALOG 0x2911
417*797c3c13SMichael Kurz 
418*797c3c13SMichael Kurz #define STM32F746_PC10_FUNC_GPIO 0x2a00
419*797c3c13SMichael Kurz #define STM32F746_PC10_FUNC_SPI3_SCK_I2S3_CK 0x2a07
420*797c3c13SMichael Kurz #define STM32F746_PC10_FUNC_USART3_TX 0x2a08
421*797c3c13SMichael Kurz #define STM32F746_PC10_FUNC_UART4_TX 0x2a09
422*797c3c13SMichael Kurz #define STM32F746_PC10_FUNC_QUADSPI_BK1_IO1 0x2a0a
423*797c3c13SMichael Kurz #define STM32F746_PC10_FUNC_SDMMC1_D2 0x2a0d
424*797c3c13SMichael Kurz #define STM32F746_PC10_FUNC_DCMI_D8 0x2a0e
425*797c3c13SMichael Kurz #define STM32F746_PC10_FUNC_LCD_R2 0x2a0f
426*797c3c13SMichael Kurz #define STM32F746_PC10_FUNC_EVENTOUT 0x2a10
427*797c3c13SMichael Kurz #define STM32F746_PC10_FUNC_ANALOG 0x2a11
428*797c3c13SMichael Kurz 
429*797c3c13SMichael Kurz #define STM32F746_PC11_FUNC_GPIO 0x2b00
430*797c3c13SMichael Kurz #define STM32F746_PC11_FUNC_SPI3_MISO 0x2b07
431*797c3c13SMichael Kurz #define STM32F746_PC11_FUNC_USART3_RX 0x2b08
432*797c3c13SMichael Kurz #define STM32F746_PC11_FUNC_UART4_RX 0x2b09
433*797c3c13SMichael Kurz #define STM32F746_PC11_FUNC_QUADSPI_BK2_NCS 0x2b0a
434*797c3c13SMichael Kurz #define STM32F746_PC11_FUNC_SDMMC1_D3 0x2b0d
435*797c3c13SMichael Kurz #define STM32F746_PC11_FUNC_DCMI_D4 0x2b0e
436*797c3c13SMichael Kurz #define STM32F746_PC11_FUNC_EVENTOUT 0x2b10
437*797c3c13SMichael Kurz #define STM32F746_PC11_FUNC_ANALOG 0x2b11
438*797c3c13SMichael Kurz 
439*797c3c13SMichael Kurz #define STM32F746_PC12_FUNC_GPIO 0x2c00
440*797c3c13SMichael Kurz #define STM32F746_PC12_FUNC_TRACED3 0x2c01
441*797c3c13SMichael Kurz #define STM32F746_PC12_FUNC_SPI3_MOSI_I2S3_SD 0x2c07
442*797c3c13SMichael Kurz #define STM32F746_PC12_FUNC_USART3_CK 0x2c08
443*797c3c13SMichael Kurz #define STM32F746_PC12_FUNC_UART5_TX 0x2c09
444*797c3c13SMichael Kurz #define STM32F746_PC12_FUNC_SDMMC1_CK 0x2c0d
445*797c3c13SMichael Kurz #define STM32F746_PC12_FUNC_DCMI_D9 0x2c0e
446*797c3c13SMichael Kurz #define STM32F746_PC12_FUNC_EVENTOUT 0x2c10
447*797c3c13SMichael Kurz #define STM32F746_PC12_FUNC_ANALOG 0x2c11
448*797c3c13SMichael Kurz 
449*797c3c13SMichael Kurz #define STM32F746_PC13_FUNC_GPIO 0x2d00
450*797c3c13SMichael Kurz #define STM32F746_PC13_FUNC_EVENTOUT 0x2d10
451*797c3c13SMichael Kurz #define STM32F746_PC13_FUNC_ANALOG 0x2d11
452*797c3c13SMichael Kurz 
453*797c3c13SMichael Kurz #define STM32F746_PC14_FUNC_GPIO 0x2e00
454*797c3c13SMichael Kurz #define STM32F746_PC14_FUNC_EVENTOUT 0x2e10
455*797c3c13SMichael Kurz #define STM32F746_PC14_FUNC_ANALOG 0x2e11
456*797c3c13SMichael Kurz 
457*797c3c13SMichael Kurz #define STM32F746_PC15_FUNC_GPIO 0x2f00
458*797c3c13SMichael Kurz #define STM32F746_PC15_FUNC_EVENTOUT 0x2f10
459*797c3c13SMichael Kurz #define STM32F746_PC15_FUNC_ANALOG 0x2f11
460*797c3c13SMichael Kurz 
461*797c3c13SMichael Kurz 
462*797c3c13SMichael Kurz #define STM32F746_PD0_FUNC_GPIO 0x3000
463*797c3c13SMichael Kurz #define STM32F746_PD0_FUNC_CAN1_RX 0x300a
464*797c3c13SMichael Kurz #define STM32F746_PD0_FUNC_FMC_D2 0x300d
465*797c3c13SMichael Kurz #define STM32F746_PD0_FUNC_EVENTOUT 0x3010
466*797c3c13SMichael Kurz #define STM32F746_PD0_FUNC_ANALOG 0x3011
467*797c3c13SMichael Kurz 
468*797c3c13SMichael Kurz #define STM32F746_PD1_FUNC_GPIO 0x3100
469*797c3c13SMichael Kurz #define STM32F746_PD1_FUNC_CAN1_TX 0x310a
470*797c3c13SMichael Kurz #define STM32F746_PD1_FUNC_FMC_D3 0x310d
471*797c3c13SMichael Kurz #define STM32F746_PD1_FUNC_EVENTOUT 0x3110
472*797c3c13SMichael Kurz #define STM32F746_PD1_FUNC_ANALOG 0x3111
473*797c3c13SMichael Kurz 
474*797c3c13SMichael Kurz #define STM32F746_PD2_FUNC_GPIO 0x3200
475*797c3c13SMichael Kurz #define STM32F746_PD2_FUNC_TRACED2 0x3201
476*797c3c13SMichael Kurz #define STM32F746_PD2_FUNC_TIM3_ETR 0x3203
477*797c3c13SMichael Kurz #define STM32F746_PD2_FUNC_UART5_RX 0x3209
478*797c3c13SMichael Kurz #define STM32F746_PD2_FUNC_SDMMC1_CMD 0x320d
479*797c3c13SMichael Kurz #define STM32F746_PD2_FUNC_DCMI_D11 0x320e
480*797c3c13SMichael Kurz #define STM32F746_PD2_FUNC_EVENTOUT 0x3210
481*797c3c13SMichael Kurz #define STM32F746_PD2_FUNC_ANALOG 0x3211
482*797c3c13SMichael Kurz 
483*797c3c13SMichael Kurz #define STM32F746_PD3_FUNC_GPIO 0x3300
484*797c3c13SMichael Kurz #define STM32F746_PD3_FUNC_SPI2_SCK_I2S2_CK 0x3306
485*797c3c13SMichael Kurz #define STM32F746_PD3_FUNC_USART2_CTS 0x3308
486*797c3c13SMichael Kurz #define STM32F746_PD3_FUNC_FMC_CLK 0x330d
487*797c3c13SMichael Kurz #define STM32F746_PD3_FUNC_DCMI_D5 0x330e
488*797c3c13SMichael Kurz #define STM32F746_PD3_FUNC_LCD_G7 0x330f
489*797c3c13SMichael Kurz #define STM32F746_PD3_FUNC_EVENTOUT 0x3310
490*797c3c13SMichael Kurz #define STM32F746_PD3_FUNC_ANALOG 0x3311
491*797c3c13SMichael Kurz 
492*797c3c13SMichael Kurz #define STM32F746_PD4_FUNC_GPIO 0x3400
493*797c3c13SMichael Kurz #define STM32F746_PD4_FUNC_USART2_RTS 0x3408
494*797c3c13SMichael Kurz #define STM32F746_PD4_FUNC_FMC_NOE 0x340d
495*797c3c13SMichael Kurz #define STM32F746_PD4_FUNC_EVENTOUT 0x3410
496*797c3c13SMichael Kurz #define STM32F746_PD4_FUNC_ANALOG 0x3411
497*797c3c13SMichael Kurz 
498*797c3c13SMichael Kurz #define STM32F746_PD5_FUNC_GPIO 0x3500
499*797c3c13SMichael Kurz #define STM32F746_PD5_FUNC_USART2_TX 0x3508
500*797c3c13SMichael Kurz #define STM32F746_PD5_FUNC_FMC_NWE 0x350d
501*797c3c13SMichael Kurz #define STM32F746_PD5_FUNC_EVENTOUT 0x3510
502*797c3c13SMichael Kurz #define STM32F746_PD5_FUNC_ANALOG 0x3511
503*797c3c13SMichael Kurz 
504*797c3c13SMichael Kurz #define STM32F746_PD6_FUNC_GPIO 0x3600
505*797c3c13SMichael Kurz #define STM32F746_PD6_FUNC_SPI3_MOSI_I2S3_SD 0x3606
506*797c3c13SMichael Kurz #define STM32F746_PD6_FUNC_SAI1_SD_A 0x3607
507*797c3c13SMichael Kurz #define STM32F746_PD6_FUNC_USART2_RX 0x3608
508*797c3c13SMichael Kurz #define STM32F746_PD6_FUNC_FMC_NWAIT 0x360d
509*797c3c13SMichael Kurz #define STM32F746_PD6_FUNC_DCMI_D10 0x360e
510*797c3c13SMichael Kurz #define STM32F746_PD6_FUNC_LCD_B2 0x360f
511*797c3c13SMichael Kurz #define STM32F746_PD6_FUNC_EVENTOUT 0x3610
512*797c3c13SMichael Kurz #define STM32F746_PD6_FUNC_ANALOG 0x3611
513*797c3c13SMichael Kurz 
514*797c3c13SMichael Kurz #define STM32F746_PD7_FUNC_GPIO 0x3700
515*797c3c13SMichael Kurz #define STM32F746_PD7_FUNC_USART2_CK 0x3708
516*797c3c13SMichael Kurz #define STM32F746_PD7_FUNC_SPDIFRX_IN0 0x3709
517*797c3c13SMichael Kurz #define STM32F746_PD7_FUNC_FMC_NE1 0x370d
518*797c3c13SMichael Kurz #define STM32F746_PD7_FUNC_EVENTOUT 0x3710
519*797c3c13SMichael Kurz #define STM32F746_PD7_FUNC_ANALOG 0x3711
520*797c3c13SMichael Kurz 
521*797c3c13SMichael Kurz #define STM32F746_PD8_FUNC_GPIO 0x3800
522*797c3c13SMichael Kurz #define STM32F746_PD8_FUNC_USART3_TX 0x3808
523*797c3c13SMichael Kurz #define STM32F746_PD8_FUNC_SPDIFRX_IN1 0x3809
524*797c3c13SMichael Kurz #define STM32F746_PD8_FUNC_FMC_D13 0x380d
525*797c3c13SMichael Kurz #define STM32F746_PD8_FUNC_EVENTOUT 0x3810
526*797c3c13SMichael Kurz #define STM32F746_PD8_FUNC_ANALOG 0x3811
527*797c3c13SMichael Kurz 
528*797c3c13SMichael Kurz #define STM32F746_PD9_FUNC_GPIO 0x3900
529*797c3c13SMichael Kurz #define STM32F746_PD9_FUNC_USART3_RX 0x3908
530*797c3c13SMichael Kurz #define STM32F746_PD9_FUNC_FMC_D14 0x390d
531*797c3c13SMichael Kurz #define STM32F746_PD9_FUNC_EVENTOUT 0x3910
532*797c3c13SMichael Kurz #define STM32F746_PD9_FUNC_ANALOG 0x3911
533*797c3c13SMichael Kurz 
534*797c3c13SMichael Kurz #define STM32F746_PD10_FUNC_GPIO 0x3a00
535*797c3c13SMichael Kurz #define STM32F746_PD10_FUNC_USART3_CK 0x3a08
536*797c3c13SMichael Kurz #define STM32F746_PD10_FUNC_FMC_D15 0x3a0d
537*797c3c13SMichael Kurz #define STM32F746_PD10_FUNC_LCD_B3 0x3a0f
538*797c3c13SMichael Kurz #define STM32F746_PD10_FUNC_EVENTOUT 0x3a10
539*797c3c13SMichael Kurz #define STM32F746_PD10_FUNC_ANALOG 0x3a11
540*797c3c13SMichael Kurz 
541*797c3c13SMichael Kurz #define STM32F746_PD11_FUNC_GPIO 0x3b00
542*797c3c13SMichael Kurz #define STM32F746_PD11_FUNC_I2C4_SMBA 0x3b05
543*797c3c13SMichael Kurz #define STM32F746_PD11_FUNC_USART3_CTS 0x3b08
544*797c3c13SMichael Kurz #define STM32F746_PD11_FUNC_QUADSPI_BK1_IO0 0x3b0a
545*797c3c13SMichael Kurz #define STM32F746_PD11_FUNC_SAI2_SD_A 0x3b0b
546*797c3c13SMichael Kurz #define STM32F746_PD11_FUNC_FMC_A16_FMC_CLE 0x3b0d
547*797c3c13SMichael Kurz #define STM32F746_PD11_FUNC_EVENTOUT 0x3b10
548*797c3c13SMichael Kurz #define STM32F746_PD11_FUNC_ANALOG 0x3b11
549*797c3c13SMichael Kurz 
550*797c3c13SMichael Kurz #define STM32F746_PD12_FUNC_GPIO 0x3c00
551*797c3c13SMichael Kurz #define STM32F746_PD12_FUNC_TIM4_CH1 0x3c03
552*797c3c13SMichael Kurz #define STM32F746_PD12_FUNC_LPTIM1_IN1 0x3c04
553*797c3c13SMichael Kurz #define STM32F746_PD12_FUNC_I2C4_SCL 0x3c05
554*797c3c13SMichael Kurz #define STM32F746_PD12_FUNC_USART3_RTS 0x3c08
555*797c3c13SMichael Kurz #define STM32F746_PD12_FUNC_QUADSPI_BK1_IO1 0x3c0a
556*797c3c13SMichael Kurz #define STM32F746_PD12_FUNC_SAI2_FS_A 0x3c0b
557*797c3c13SMichael Kurz #define STM32F746_PD12_FUNC_FMC_A17_FMC_ALE 0x3c0d
558*797c3c13SMichael Kurz #define STM32F746_PD12_FUNC_EVENTOUT 0x3c10
559*797c3c13SMichael Kurz #define STM32F746_PD12_FUNC_ANALOG 0x3c11
560*797c3c13SMichael Kurz 
561*797c3c13SMichael Kurz #define STM32F746_PD13_FUNC_GPIO 0x3d00
562*797c3c13SMichael Kurz #define STM32F746_PD13_FUNC_TIM4_CH2 0x3d03
563*797c3c13SMichael Kurz #define STM32F746_PD13_FUNC_LPTIM1_OUT 0x3d04
564*797c3c13SMichael Kurz #define STM32F746_PD13_FUNC_I2C4_SDA 0x3d05
565*797c3c13SMichael Kurz #define STM32F746_PD13_FUNC_QUADSPI_BK1_IO3 0x3d0a
566*797c3c13SMichael Kurz #define STM32F746_PD13_FUNC_SAI2_SCK_A 0x3d0b
567*797c3c13SMichael Kurz #define STM32F746_PD13_FUNC_FMC_A18 0x3d0d
568*797c3c13SMichael Kurz #define STM32F746_PD13_FUNC_EVENTOUT 0x3d10
569*797c3c13SMichael Kurz #define STM32F746_PD13_FUNC_ANALOG 0x3d11
570*797c3c13SMichael Kurz 
571*797c3c13SMichael Kurz #define STM32F746_PD14_FUNC_GPIO 0x3e00
572*797c3c13SMichael Kurz #define STM32F746_PD14_FUNC_TIM4_CH3 0x3e03
573*797c3c13SMichael Kurz #define STM32F746_PD14_FUNC_UART8_CTS 0x3e09
574*797c3c13SMichael Kurz #define STM32F746_PD14_FUNC_FMC_D0 0x3e0d
575*797c3c13SMichael Kurz #define STM32F746_PD14_FUNC_EVENTOUT 0x3e10
576*797c3c13SMichael Kurz #define STM32F746_PD14_FUNC_ANALOG 0x3e11
577*797c3c13SMichael Kurz 
578*797c3c13SMichael Kurz #define STM32F746_PD15_FUNC_GPIO 0x3f00
579*797c3c13SMichael Kurz #define STM32F746_PD15_FUNC_TIM4_CH4 0x3f03
580*797c3c13SMichael Kurz #define STM32F746_PD15_FUNC_UART8_RTS 0x3f09
581*797c3c13SMichael Kurz #define STM32F746_PD15_FUNC_FMC_D1 0x3f0d
582*797c3c13SMichael Kurz #define STM32F746_PD15_FUNC_EVENTOUT 0x3f10
583*797c3c13SMichael Kurz #define STM32F746_PD15_FUNC_ANALOG 0x3f11
584*797c3c13SMichael Kurz 
585*797c3c13SMichael Kurz 
586*797c3c13SMichael Kurz #define STM32F746_PE0_FUNC_GPIO 0x4000
587*797c3c13SMichael Kurz #define STM32F746_PE0_FUNC_TIM4_ETR 0x4003
588*797c3c13SMichael Kurz #define STM32F746_PE0_FUNC_LPTIM1_ETR 0x4004
589*797c3c13SMichael Kurz #define STM32F746_PE0_FUNC_UART8_RX 0x4009
590*797c3c13SMichael Kurz #define STM32F746_PE0_FUNC_SAI2_MCLK_A 0x400b
591*797c3c13SMichael Kurz #define STM32F746_PE0_FUNC_FMC_NBL0 0x400d
592*797c3c13SMichael Kurz #define STM32F746_PE0_FUNC_DCMI_D2 0x400e
593*797c3c13SMichael Kurz #define STM32F746_PE0_FUNC_EVENTOUT 0x4010
594*797c3c13SMichael Kurz #define STM32F746_PE0_FUNC_ANALOG 0x4011
595*797c3c13SMichael Kurz 
596*797c3c13SMichael Kurz #define STM32F746_PE1_FUNC_GPIO 0x4100
597*797c3c13SMichael Kurz #define STM32F746_PE1_FUNC_LPTIM1_IN2 0x4104
598*797c3c13SMichael Kurz #define STM32F746_PE1_FUNC_UART8_TX 0x4109
599*797c3c13SMichael Kurz #define STM32F746_PE1_FUNC_FMC_NBL1 0x410d
600*797c3c13SMichael Kurz #define STM32F746_PE1_FUNC_DCMI_D3 0x410e
601*797c3c13SMichael Kurz #define STM32F746_PE1_FUNC_EVENTOUT 0x4110
602*797c3c13SMichael Kurz #define STM32F746_PE1_FUNC_ANALOG 0x4111
603*797c3c13SMichael Kurz 
604*797c3c13SMichael Kurz #define STM32F746_PE2_FUNC_GPIO 0x4200
605*797c3c13SMichael Kurz #define STM32F746_PE2_FUNC_TRACECLK 0x4201
606*797c3c13SMichael Kurz #define STM32F746_PE2_FUNC_SPI4_SCK 0x4206
607*797c3c13SMichael Kurz #define STM32F746_PE2_FUNC_SAI1_MCLK_A 0x4207
608*797c3c13SMichael Kurz #define STM32F746_PE2_FUNC_QUADSPI_BK1_IO2 0x420a
609*797c3c13SMichael Kurz #define STM32F746_PE2_FUNC_ETH_MII_TXD3 0x420c
610*797c3c13SMichael Kurz #define STM32F746_PE2_FUNC_FMC_A23 0x420d
611*797c3c13SMichael Kurz #define STM32F746_PE2_FUNC_EVENTOUT 0x4210
612*797c3c13SMichael Kurz #define STM32F746_PE2_FUNC_ANALOG 0x4211
613*797c3c13SMichael Kurz 
614*797c3c13SMichael Kurz #define STM32F746_PE3_FUNC_GPIO 0x4300
615*797c3c13SMichael Kurz #define STM32F746_PE3_FUNC_TRACED0 0x4301
616*797c3c13SMichael Kurz #define STM32F746_PE3_FUNC_SAI1_SD_B 0x4307
617*797c3c13SMichael Kurz #define STM32F746_PE3_FUNC_FMC_A19 0x430d
618*797c3c13SMichael Kurz #define STM32F746_PE3_FUNC_EVENTOUT 0x4310
619*797c3c13SMichael Kurz #define STM32F746_PE3_FUNC_ANALOG 0x4311
620*797c3c13SMichael Kurz 
621*797c3c13SMichael Kurz #define STM32F746_PE4_FUNC_GPIO 0x4400
622*797c3c13SMichael Kurz #define STM32F746_PE4_FUNC_TRACED1 0x4401
623*797c3c13SMichael Kurz #define STM32F746_PE4_FUNC_SPI4_NSS 0x4406
624*797c3c13SMichael Kurz #define STM32F746_PE4_FUNC_SAI1_FS_A 0x4407
625*797c3c13SMichael Kurz #define STM32F746_PE4_FUNC_FMC_A20 0x440d
626*797c3c13SMichael Kurz #define STM32F746_PE4_FUNC_DCMI_D4 0x440e
627*797c3c13SMichael Kurz #define STM32F746_PE4_FUNC_LCD_B0 0x440f
628*797c3c13SMichael Kurz #define STM32F746_PE4_FUNC_EVENTOUT 0x4410
629*797c3c13SMichael Kurz #define STM32F746_PE4_FUNC_ANALOG 0x4411
630*797c3c13SMichael Kurz 
631*797c3c13SMichael Kurz #define STM32F746_PE5_FUNC_GPIO 0x4500
632*797c3c13SMichael Kurz #define STM32F746_PE5_FUNC_TRACED2 0x4501
633*797c3c13SMichael Kurz #define STM32F746_PE5_FUNC_TIM9_CH1 0x4504
634*797c3c13SMichael Kurz #define STM32F746_PE5_FUNC_SPI4_MISO 0x4506
635*797c3c13SMichael Kurz #define STM32F746_PE5_FUNC_SAI1_SCK_A 0x4507
636*797c3c13SMichael Kurz #define STM32F746_PE5_FUNC_FMC_A21 0x450d
637*797c3c13SMichael Kurz #define STM32F746_PE5_FUNC_DCMI_D6 0x450e
638*797c3c13SMichael Kurz #define STM32F746_PE5_FUNC_LCD_G0 0x450f
639*797c3c13SMichael Kurz #define STM32F746_PE5_FUNC_EVENTOUT 0x4510
640*797c3c13SMichael Kurz #define STM32F746_PE5_FUNC_ANALOG 0x4511
641*797c3c13SMichael Kurz 
642*797c3c13SMichael Kurz #define STM32F746_PE6_FUNC_GPIO 0x4600
643*797c3c13SMichael Kurz #define STM32F746_PE6_FUNC_TRACED3 0x4601
644*797c3c13SMichael Kurz #define STM32F746_PE6_FUNC_TIM1_BKIN2 0x4602
645*797c3c13SMichael Kurz #define STM32F746_PE6_FUNC_TIM9_CH2 0x4604
646*797c3c13SMichael Kurz #define STM32F746_PE6_FUNC_SPI4_MOSI 0x4606
647*797c3c13SMichael Kurz #define STM32F746_PE6_FUNC_SAI1_SD_A 0x4607
648*797c3c13SMichael Kurz #define STM32F746_PE6_FUNC_SAI2_MCLK_B 0x460b
649*797c3c13SMichael Kurz #define STM32F746_PE6_FUNC_FMC_A22 0x460d
650*797c3c13SMichael Kurz #define STM32F746_PE6_FUNC_DCMI_D7 0x460e
651*797c3c13SMichael Kurz #define STM32F746_PE6_FUNC_LCD_G1 0x460f
652*797c3c13SMichael Kurz #define STM32F746_PE6_FUNC_EVENTOUT 0x4610
653*797c3c13SMichael Kurz #define STM32F746_PE6_FUNC_ANALOG 0x4611
654*797c3c13SMichael Kurz 
655*797c3c13SMichael Kurz #define STM32F746_PE7_FUNC_GPIO 0x4700
656*797c3c13SMichael Kurz #define STM32F746_PE7_FUNC_TIM1_ETR 0x4702
657*797c3c13SMichael Kurz #define STM32F746_PE7_FUNC_UART7_RX 0x4709
658*797c3c13SMichael Kurz #define STM32F746_PE7_FUNC_QUADSPI_BK2_IO0 0x470b
659*797c3c13SMichael Kurz #define STM32F746_PE7_FUNC_FMC_D4 0x470d
660*797c3c13SMichael Kurz #define STM32F746_PE7_FUNC_EVENTOUT 0x4710
661*797c3c13SMichael Kurz #define STM32F746_PE7_FUNC_ANALOG 0x4711
662*797c3c13SMichael Kurz 
663*797c3c13SMichael Kurz #define STM32F746_PE8_FUNC_GPIO 0x4800
664*797c3c13SMichael Kurz #define STM32F746_PE8_FUNC_TIM1_CH1N 0x4802
665*797c3c13SMichael Kurz #define STM32F746_PE8_FUNC_UART7_TX 0x4809
666*797c3c13SMichael Kurz #define STM32F746_PE8_FUNC_QUADSPI_BK2_IO1 0x480b
667*797c3c13SMichael Kurz #define STM32F746_PE8_FUNC_FMC_D5 0x480d
668*797c3c13SMichael Kurz #define STM32F746_PE8_FUNC_EVENTOUT 0x4810
669*797c3c13SMichael Kurz #define STM32F746_PE8_FUNC_ANALOG 0x4811
670*797c3c13SMichael Kurz 
671*797c3c13SMichael Kurz #define STM32F746_PE9_FUNC_GPIO 0x4900
672*797c3c13SMichael Kurz #define STM32F746_PE9_FUNC_TIM1_CH1 0x4902
673*797c3c13SMichael Kurz #define STM32F746_PE9_FUNC_UART7_RTS 0x4909
674*797c3c13SMichael Kurz #define STM32F746_PE9_FUNC_QUADSPI_BK2_IO2 0x490b
675*797c3c13SMichael Kurz #define STM32F746_PE9_FUNC_FMC_D6 0x490d
676*797c3c13SMichael Kurz #define STM32F746_PE9_FUNC_EVENTOUT 0x4910
677*797c3c13SMichael Kurz #define STM32F746_PE9_FUNC_ANALOG 0x4911
678*797c3c13SMichael Kurz 
679*797c3c13SMichael Kurz #define STM32F746_PE10_FUNC_GPIO 0x4a00
680*797c3c13SMichael Kurz #define STM32F746_PE10_FUNC_TIM1_CH2N 0x4a02
681*797c3c13SMichael Kurz #define STM32F746_PE10_FUNC_UART7_CTS 0x4a09
682*797c3c13SMichael Kurz #define STM32F746_PE10_FUNC_QUADSPI_BK2_IO3 0x4a0b
683*797c3c13SMichael Kurz #define STM32F746_PE10_FUNC_FMC_D7 0x4a0d
684*797c3c13SMichael Kurz #define STM32F746_PE10_FUNC_EVENTOUT 0x4a10
685*797c3c13SMichael Kurz #define STM32F746_PE10_FUNC_ANALOG 0x4a11
686*797c3c13SMichael Kurz 
687*797c3c13SMichael Kurz #define STM32F746_PE11_FUNC_GPIO 0x4b00
688*797c3c13SMichael Kurz #define STM32F746_PE11_FUNC_TIM1_CH2 0x4b02
689*797c3c13SMichael Kurz #define STM32F746_PE11_FUNC_SPI4_NSS 0x4b06
690*797c3c13SMichael Kurz #define STM32F746_PE11_FUNC_SAI2_SD_B 0x4b0b
691*797c3c13SMichael Kurz #define STM32F746_PE11_FUNC_FMC_D8 0x4b0d
692*797c3c13SMichael Kurz #define STM32F746_PE11_FUNC_LCD_G3 0x4b0f
693*797c3c13SMichael Kurz #define STM32F746_PE11_FUNC_EVENTOUT 0x4b10
694*797c3c13SMichael Kurz #define STM32F746_PE11_FUNC_ANALOG 0x4b11
695*797c3c13SMichael Kurz 
696*797c3c13SMichael Kurz #define STM32F746_PE12_FUNC_GPIO 0x4c00
697*797c3c13SMichael Kurz #define STM32F746_PE12_FUNC_TIM1_CH3N 0x4c02
698*797c3c13SMichael Kurz #define STM32F746_PE12_FUNC_SPI4_SCK 0x4c06
699*797c3c13SMichael Kurz #define STM32F746_PE12_FUNC_SAI2_SCK_B 0x4c0b
700*797c3c13SMichael Kurz #define STM32F746_PE12_FUNC_FMC_D9 0x4c0d
701*797c3c13SMichael Kurz #define STM32F746_PE12_FUNC_LCD_B4 0x4c0f
702*797c3c13SMichael Kurz #define STM32F746_PE12_FUNC_EVENTOUT 0x4c10
703*797c3c13SMichael Kurz #define STM32F746_PE12_FUNC_ANALOG 0x4c11
704*797c3c13SMichael Kurz 
705*797c3c13SMichael Kurz #define STM32F746_PE13_FUNC_GPIO 0x4d00
706*797c3c13SMichael Kurz #define STM32F746_PE13_FUNC_TIM1_CH3 0x4d02
707*797c3c13SMichael Kurz #define STM32F746_PE13_FUNC_SPI4_MISO 0x4d06
708*797c3c13SMichael Kurz #define STM32F746_PE13_FUNC_SAI2_FS_B 0x4d0b
709*797c3c13SMichael Kurz #define STM32F746_PE13_FUNC_FMC_D10 0x4d0d
710*797c3c13SMichael Kurz #define STM32F746_PE13_FUNC_LCD_DE 0x4d0f
711*797c3c13SMichael Kurz #define STM32F746_PE13_FUNC_EVENTOUT 0x4d10
712*797c3c13SMichael Kurz #define STM32F746_PE13_FUNC_ANALOG 0x4d11
713*797c3c13SMichael Kurz 
714*797c3c13SMichael Kurz #define STM32F746_PE14_FUNC_GPIO 0x4e00
715*797c3c13SMichael Kurz #define STM32F746_PE14_FUNC_TIM1_CH4 0x4e02
716*797c3c13SMichael Kurz #define STM32F746_PE14_FUNC_SPI4_MOSI 0x4e06
717*797c3c13SMichael Kurz #define STM32F746_PE14_FUNC_SAI2_MCLK_B 0x4e0b
718*797c3c13SMichael Kurz #define STM32F746_PE14_FUNC_FMC_D11 0x4e0d
719*797c3c13SMichael Kurz #define STM32F746_PE14_FUNC_LCD_CLK 0x4e0f
720*797c3c13SMichael Kurz #define STM32F746_PE14_FUNC_EVENTOUT 0x4e10
721*797c3c13SMichael Kurz #define STM32F746_PE14_FUNC_ANALOG 0x4e11
722*797c3c13SMichael Kurz 
723*797c3c13SMichael Kurz #define STM32F746_PE15_FUNC_GPIO 0x4f00
724*797c3c13SMichael Kurz #define STM32F746_PE15_FUNC_TIM1_BKIN 0x4f02
725*797c3c13SMichael Kurz #define STM32F746_PE15_FUNC_FMC_D12 0x4f0d
726*797c3c13SMichael Kurz #define STM32F746_PE15_FUNC_LCD_R7 0x4f0f
727*797c3c13SMichael Kurz #define STM32F746_PE15_FUNC_EVENTOUT 0x4f10
728*797c3c13SMichael Kurz #define STM32F746_PE15_FUNC_ANALOG 0x4f11
729*797c3c13SMichael Kurz 
730*797c3c13SMichael Kurz 
731*797c3c13SMichael Kurz #define STM32F746_PF0_FUNC_GPIO 0x5000
732*797c3c13SMichael Kurz #define STM32F746_PF0_FUNC_I2C2_SDA 0x5005
733*797c3c13SMichael Kurz #define STM32F746_PF0_FUNC_FMC_A0 0x500d
734*797c3c13SMichael Kurz #define STM32F746_PF0_FUNC_EVENTOUT 0x5010
735*797c3c13SMichael Kurz #define STM32F746_PF0_FUNC_ANALOG 0x5011
736*797c3c13SMichael Kurz 
737*797c3c13SMichael Kurz #define STM32F746_PF1_FUNC_GPIO 0x5100
738*797c3c13SMichael Kurz #define STM32F746_PF1_FUNC_I2C2_SCL 0x5105
739*797c3c13SMichael Kurz #define STM32F746_PF1_FUNC_FMC_A1 0x510d
740*797c3c13SMichael Kurz #define STM32F746_PF1_FUNC_EVENTOUT 0x5110
741*797c3c13SMichael Kurz #define STM32F746_PF1_FUNC_ANALOG 0x5111
742*797c3c13SMichael Kurz 
743*797c3c13SMichael Kurz #define STM32F746_PF2_FUNC_GPIO 0x5200
744*797c3c13SMichael Kurz #define STM32F746_PF2_FUNC_I2C2_SMBA 0x5205
745*797c3c13SMichael Kurz #define STM32F746_PF2_FUNC_FMC_A2 0x520d
746*797c3c13SMichael Kurz #define STM32F746_PF2_FUNC_EVENTOUT 0x5210
747*797c3c13SMichael Kurz #define STM32F746_PF2_FUNC_ANALOG 0x5211
748*797c3c13SMichael Kurz 
749*797c3c13SMichael Kurz #define STM32F746_PF3_FUNC_GPIO 0x5300
750*797c3c13SMichael Kurz #define STM32F746_PF3_FUNC_FMC_A3 0x530d
751*797c3c13SMichael Kurz #define STM32F746_PF3_FUNC_EVENTOUT 0x5310
752*797c3c13SMichael Kurz #define STM32F746_PF3_FUNC_ANALOG 0x5311
753*797c3c13SMichael Kurz 
754*797c3c13SMichael Kurz #define STM32F746_PF4_FUNC_GPIO 0x5400
755*797c3c13SMichael Kurz #define STM32F746_PF4_FUNC_FMC_A4 0x540d
756*797c3c13SMichael Kurz #define STM32F746_PF4_FUNC_EVENTOUT 0x5410
757*797c3c13SMichael Kurz #define STM32F746_PF4_FUNC_ANALOG 0x5411
758*797c3c13SMichael Kurz 
759*797c3c13SMichael Kurz #define STM32F746_PF5_FUNC_GPIO 0x5500
760*797c3c13SMichael Kurz #define STM32F746_PF5_FUNC_FMC_A5 0x550d
761*797c3c13SMichael Kurz #define STM32F746_PF5_FUNC_EVENTOUT 0x5510
762*797c3c13SMichael Kurz #define STM32F746_PF5_FUNC_ANALOG 0x5511
763*797c3c13SMichael Kurz 
764*797c3c13SMichael Kurz #define STM32F746_PF6_FUNC_GPIO 0x5600
765*797c3c13SMichael Kurz #define STM32F746_PF6_FUNC_TIM10_CH1 0x5604
766*797c3c13SMichael Kurz #define STM32F746_PF6_FUNC_SPI5_NSS 0x5606
767*797c3c13SMichael Kurz #define STM32F746_PF6_FUNC_SAI1_SD_B 0x5607
768*797c3c13SMichael Kurz #define STM32F746_PF6_FUNC_UART7_RX 0x5609
769*797c3c13SMichael Kurz #define STM32F746_PF6_FUNC_QUADSPI_BK1_IO3 0x560a
770*797c3c13SMichael Kurz #define STM32F746_PF6_FUNC_EVENTOUT 0x5610
771*797c3c13SMichael Kurz #define STM32F746_PF6_FUNC_ANALOG 0x5611
772*797c3c13SMichael Kurz 
773*797c3c13SMichael Kurz #define STM32F746_PF7_FUNC_GPIO 0x5700
774*797c3c13SMichael Kurz #define STM32F746_PF7_FUNC_TIM11_CH1 0x5704
775*797c3c13SMichael Kurz #define STM32F746_PF7_FUNC_SPI5_SCK 0x5706
776*797c3c13SMichael Kurz #define STM32F746_PF7_FUNC_SAI1_MCLK_B 0x5707
777*797c3c13SMichael Kurz #define STM32F746_PF7_FUNC_UART7_TX 0x5709
778*797c3c13SMichael Kurz #define STM32F746_PF7_FUNC_QUADSPI_BK1_IO2 0x570a
779*797c3c13SMichael Kurz #define STM32F746_PF7_FUNC_EVENTOUT 0x5710
780*797c3c13SMichael Kurz #define STM32F746_PF7_FUNC_ANALOG 0x5711
781*797c3c13SMichael Kurz 
782*797c3c13SMichael Kurz #define STM32F746_PF8_FUNC_GPIO 0x5800
783*797c3c13SMichael Kurz #define STM32F746_PF8_FUNC_SPI5_MISO 0x5806
784*797c3c13SMichael Kurz #define STM32F746_PF8_FUNC_SAI1_SCK_B 0x5807
785*797c3c13SMichael Kurz #define STM32F746_PF8_FUNC_UART7_RTS 0x5809
786*797c3c13SMichael Kurz #define STM32F746_PF8_FUNC_TIM13_CH1 0x580a
787*797c3c13SMichael Kurz #define STM32F746_PF8_FUNC_QUADSPI_BK1_IO0 0x580b
788*797c3c13SMichael Kurz #define STM32F746_PF8_FUNC_EVENTOUT 0x5810
789*797c3c13SMichael Kurz #define STM32F746_PF8_FUNC_ANALOG 0x5811
790*797c3c13SMichael Kurz 
791*797c3c13SMichael Kurz #define STM32F746_PF9_FUNC_GPIO 0x5900
792*797c3c13SMichael Kurz #define STM32F746_PF9_FUNC_SPI5_MOSI 0x5906
793*797c3c13SMichael Kurz #define STM32F746_PF9_FUNC_SAI1_FS_B 0x5907
794*797c3c13SMichael Kurz #define STM32F746_PF9_FUNC_UART7_CTS 0x5909
795*797c3c13SMichael Kurz #define STM32F746_PF9_FUNC_TIM14_CH1 0x590a
796*797c3c13SMichael Kurz #define STM32F746_PF9_FUNC_QUADSPI_BK1_IO1 0x590b
797*797c3c13SMichael Kurz #define STM32F746_PF9_FUNC_EVENTOUT 0x5910
798*797c3c13SMichael Kurz #define STM32F746_PF9_FUNC_ANALOG 0x5911
799*797c3c13SMichael Kurz 
800*797c3c13SMichael Kurz #define STM32F746_PF10_FUNC_GPIO 0x5a00
801*797c3c13SMichael Kurz #define STM32F746_PF10_FUNC_DCMI_D11 0x5a0e
802*797c3c13SMichael Kurz #define STM32F746_PF10_FUNC_LCD_DE 0x5a0f
803*797c3c13SMichael Kurz #define STM32F746_PF10_FUNC_EVENTOUT 0x5a10
804*797c3c13SMichael Kurz #define STM32F746_PF10_FUNC_ANALOG 0x5a11
805*797c3c13SMichael Kurz 
806*797c3c13SMichael Kurz #define STM32F746_PF11_FUNC_GPIO 0x5b00
807*797c3c13SMichael Kurz #define STM32F746_PF11_FUNC_SPI5_MOSI 0x5b06
808*797c3c13SMichael Kurz #define STM32F746_PF11_FUNC_SAI2_SD_B 0x5b0b
809*797c3c13SMichael Kurz #define STM32F746_PF11_FUNC_FMC_SDNRAS 0x5b0d
810*797c3c13SMichael Kurz #define STM32F746_PF11_FUNC_DCMI_D12 0x5b0e
811*797c3c13SMichael Kurz #define STM32F746_PF11_FUNC_EVENTOUT 0x5b10
812*797c3c13SMichael Kurz #define STM32F746_PF11_FUNC_ANALOG 0x5b11
813*797c3c13SMichael Kurz 
814*797c3c13SMichael Kurz #define STM32F746_PF12_FUNC_GPIO 0x5c00
815*797c3c13SMichael Kurz #define STM32F746_PF12_FUNC_FMC_A6 0x5c0d
816*797c3c13SMichael Kurz #define STM32F746_PF12_FUNC_EVENTOUT 0x5c10
817*797c3c13SMichael Kurz #define STM32F746_PF12_FUNC_ANALOG 0x5c11
818*797c3c13SMichael Kurz 
819*797c3c13SMichael Kurz #define STM32F746_PF13_FUNC_GPIO 0x5d00
820*797c3c13SMichael Kurz #define STM32F746_PF13_FUNC_I2C4_SMBA 0x5d05
821*797c3c13SMichael Kurz #define STM32F746_PF13_FUNC_FMC_A7 0x5d0d
822*797c3c13SMichael Kurz #define STM32F746_PF13_FUNC_EVENTOUT 0x5d10
823*797c3c13SMichael Kurz #define STM32F746_PF13_FUNC_ANALOG 0x5d11
824*797c3c13SMichael Kurz 
825*797c3c13SMichael Kurz #define STM32F746_PF14_FUNC_GPIO 0x5e00
826*797c3c13SMichael Kurz #define STM32F746_PF14_FUNC_I2C4_SCL 0x5e05
827*797c3c13SMichael Kurz #define STM32F746_PF14_FUNC_FMC_A8 0x5e0d
828*797c3c13SMichael Kurz #define STM32F746_PF14_FUNC_EVENTOUT 0x5e10
829*797c3c13SMichael Kurz #define STM32F746_PF14_FUNC_ANALOG 0x5e11
830*797c3c13SMichael Kurz 
831*797c3c13SMichael Kurz #define STM32F746_PF15_FUNC_GPIO 0x5f00
832*797c3c13SMichael Kurz #define STM32F746_PF15_FUNC_I2C4_SDA 0x5f05
833*797c3c13SMichael Kurz #define STM32F746_PF15_FUNC_FMC_A9 0x5f0d
834*797c3c13SMichael Kurz #define STM32F746_PF15_FUNC_EVENTOUT 0x5f10
835*797c3c13SMichael Kurz #define STM32F746_PF15_FUNC_ANALOG 0x5f11
836*797c3c13SMichael Kurz 
837*797c3c13SMichael Kurz 
838*797c3c13SMichael Kurz #define STM32F746_PG0_FUNC_GPIO 0x6000
839*797c3c13SMichael Kurz #define STM32F746_PG0_FUNC_FMC_A10 0x600d
840*797c3c13SMichael Kurz #define STM32F746_PG0_FUNC_EVENTOUT 0x6010
841*797c3c13SMichael Kurz #define STM32F746_PG0_FUNC_ANALOG 0x6011
842*797c3c13SMichael Kurz 
843*797c3c13SMichael Kurz #define STM32F746_PG1_FUNC_GPIO 0x6100
844*797c3c13SMichael Kurz #define STM32F746_PG1_FUNC_FMC_A11 0x610d
845*797c3c13SMichael Kurz #define STM32F746_PG1_FUNC_EVENTOUT 0x6110
846*797c3c13SMichael Kurz #define STM32F746_PG1_FUNC_ANALOG 0x6111
847*797c3c13SMichael Kurz 
848*797c3c13SMichael Kurz #define STM32F746_PG2_FUNC_GPIO 0x6200
849*797c3c13SMichael Kurz #define STM32F746_PG2_FUNC_FMC_A12 0x620d
850*797c3c13SMichael Kurz #define STM32F746_PG2_FUNC_EVENTOUT 0x6210
851*797c3c13SMichael Kurz #define STM32F746_PG2_FUNC_ANALOG 0x6211
852*797c3c13SMichael Kurz 
853*797c3c13SMichael Kurz #define STM32F746_PG3_FUNC_GPIO 0x6300
854*797c3c13SMichael Kurz #define STM32F746_PG3_FUNC_FMC_A13 0x630d
855*797c3c13SMichael Kurz #define STM32F746_PG3_FUNC_EVENTOUT 0x6310
856*797c3c13SMichael Kurz #define STM32F746_PG3_FUNC_ANALOG 0x6311
857*797c3c13SMichael Kurz 
858*797c3c13SMichael Kurz #define STM32F746_PG4_FUNC_GPIO 0x6400
859*797c3c13SMichael Kurz #define STM32F746_PG4_FUNC_FMC_A14_FMC_BA0 0x640d
860*797c3c13SMichael Kurz #define STM32F746_PG4_FUNC_EVENTOUT 0x6410
861*797c3c13SMichael Kurz #define STM32F746_PG4_FUNC_ANALOG 0x6411
862*797c3c13SMichael Kurz 
863*797c3c13SMichael Kurz #define STM32F746_PG5_FUNC_GPIO 0x6500
864*797c3c13SMichael Kurz #define STM32F746_PG5_FUNC_FMC_A15_FMC_BA1 0x650d
865*797c3c13SMichael Kurz #define STM32F746_PG5_FUNC_EVENTOUT 0x6510
866*797c3c13SMichael Kurz #define STM32F746_PG5_FUNC_ANALOG 0x6511
867*797c3c13SMichael Kurz 
868*797c3c13SMichael Kurz #define STM32F746_PG6_FUNC_GPIO 0x6600
869*797c3c13SMichael Kurz #define STM32F746_PG6_FUNC_DCMI_D12 0x660e
870*797c3c13SMichael Kurz #define STM32F746_PG6_FUNC_LCD_R7 0x660f
871*797c3c13SMichael Kurz #define STM32F746_PG6_FUNC_EVENTOUT 0x6610
872*797c3c13SMichael Kurz #define STM32F746_PG6_FUNC_ANALOG 0x6611
873*797c3c13SMichael Kurz 
874*797c3c13SMichael Kurz #define STM32F746_PG7_FUNC_GPIO 0x6700
875*797c3c13SMichael Kurz #define STM32F746_PG7_FUNC_USART6_CK 0x6709
876*797c3c13SMichael Kurz #define STM32F746_PG7_FUNC_FMC_INT 0x670d
877*797c3c13SMichael Kurz #define STM32F746_PG7_FUNC_DCMI_D13 0x670e
878*797c3c13SMichael Kurz #define STM32F746_PG7_FUNC_LCD_CLK 0x670f
879*797c3c13SMichael Kurz #define STM32F746_PG7_FUNC_EVENTOUT 0x6710
880*797c3c13SMichael Kurz #define STM32F746_PG7_FUNC_ANALOG 0x6711
881*797c3c13SMichael Kurz 
882*797c3c13SMichael Kurz #define STM32F746_PG8_FUNC_GPIO 0x6800
883*797c3c13SMichael Kurz #define STM32F746_PG8_FUNC_SPI6_NSS 0x6806
884*797c3c13SMichael Kurz #define STM32F746_PG8_FUNC_SPDIFRX_IN2 0x6808
885*797c3c13SMichael Kurz #define STM32F746_PG8_FUNC_USART6_RTS 0x6809
886*797c3c13SMichael Kurz #define STM32F746_PG8_FUNC_ETH_PPS_OUT 0x680c
887*797c3c13SMichael Kurz #define STM32F746_PG8_FUNC_FMC_SDCLK 0x680d
888*797c3c13SMichael Kurz #define STM32F746_PG8_FUNC_EVENTOUT 0x6810
889*797c3c13SMichael Kurz #define STM32F746_PG8_FUNC_ANALOG 0x6811
890*797c3c13SMichael Kurz 
891*797c3c13SMichael Kurz #define STM32F746_PG9_FUNC_GPIO 0x6900
892*797c3c13SMichael Kurz #define STM32F746_PG9_FUNC_SPDIFRX_IN3 0x6908
893*797c3c13SMichael Kurz #define STM32F746_PG9_FUNC_USART6_RX 0x6909
894*797c3c13SMichael Kurz #define STM32F746_PG9_FUNC_QUADSPI_BK2_IO2 0x690a
895*797c3c13SMichael Kurz #define STM32F746_PG9_FUNC_SAI2_FS_B 0x690b
896*797c3c13SMichael Kurz #define STM32F746_PG9_FUNC_FMC_NE2_FMC_NCE 0x690d
897*797c3c13SMichael Kurz #define STM32F746_PG9_FUNC_DCMI_VSYNC 0x690e
898*797c3c13SMichael Kurz #define STM32F746_PG9_FUNC_EVENTOUT 0x6910
899*797c3c13SMichael Kurz #define STM32F746_PG9_FUNC_ANALOG 0x6911
900*797c3c13SMichael Kurz 
901*797c3c13SMichael Kurz #define STM32F746_PG10_FUNC_GPIO 0x6a00
902*797c3c13SMichael Kurz #define STM32F746_PG10_FUNC_LCD_G3 0x6a0a
903*797c3c13SMichael Kurz #define STM32F746_PG10_FUNC_SAI2_SD_B 0x6a0b
904*797c3c13SMichael Kurz #define STM32F746_PG10_FUNC_FMC_NE3 0x6a0d
905*797c3c13SMichael Kurz #define STM32F746_PG10_FUNC_DCMI_D2 0x6a0e
906*797c3c13SMichael Kurz #define STM32F746_PG10_FUNC_LCD_B2 0x6a0f
907*797c3c13SMichael Kurz #define STM32F746_PG10_FUNC_EVENTOUT 0x6a10
908*797c3c13SMichael Kurz #define STM32F746_PG10_FUNC_ANALOG 0x6a11
909*797c3c13SMichael Kurz 
910*797c3c13SMichael Kurz #define STM32F746_PG11_FUNC_GPIO 0x6b00
911*797c3c13SMichael Kurz #define STM32F746_PG11_FUNC_SPDIFRX_IN0 0x6b08
912*797c3c13SMichael Kurz #define STM32F746_PG11_FUNC_ETH_MII_TX_EN_ETH_RMII_TX_EN 0x6b0c
913*797c3c13SMichael Kurz #define STM32F746_PG11_FUNC_DCMI_D3 0x6b0e
914*797c3c13SMichael Kurz #define STM32F746_PG11_FUNC_LCD_B3 0x6b0f
915*797c3c13SMichael Kurz #define STM32F746_PG11_FUNC_EVENTOUT 0x6b10
916*797c3c13SMichael Kurz #define STM32F746_PG11_FUNC_ANALOG 0x6b11
917*797c3c13SMichael Kurz 
918*797c3c13SMichael Kurz #define STM32F746_PG12_FUNC_GPIO 0x6c00
919*797c3c13SMichael Kurz #define STM32F746_PG12_FUNC_LPTIM1_IN1 0x6c04
920*797c3c13SMichael Kurz #define STM32F746_PG12_FUNC_SPI6_MISO 0x6c06
921*797c3c13SMichael Kurz #define STM32F746_PG12_FUNC_SPDIFRX_IN1 0x6c08
922*797c3c13SMichael Kurz #define STM32F746_PG12_FUNC_USART6_RTS 0x6c09
923*797c3c13SMichael Kurz #define STM32F746_PG12_FUNC_LCD_B4 0x6c0a
924*797c3c13SMichael Kurz #define STM32F746_PG12_FUNC_FMC_NE4 0x6c0d
925*797c3c13SMichael Kurz #define STM32F746_PG12_FUNC_LCD_B1 0x6c0f
926*797c3c13SMichael Kurz #define STM32F746_PG12_FUNC_EVENTOUT 0x6c10
927*797c3c13SMichael Kurz #define STM32F746_PG12_FUNC_ANALOG 0x6c11
928*797c3c13SMichael Kurz 
929*797c3c13SMichael Kurz #define STM32F746_PG13_FUNC_GPIO 0x6d00
930*797c3c13SMichael Kurz #define STM32F746_PG13_FUNC_TRACED0 0x6d01
931*797c3c13SMichael Kurz #define STM32F746_PG13_FUNC_LPTIM1_OUT 0x6d04
932*797c3c13SMichael Kurz #define STM32F746_PG13_FUNC_SPI6_SCK 0x6d06
933*797c3c13SMichael Kurz #define STM32F746_PG13_FUNC_USART6_CTS 0x6d09
934*797c3c13SMichael Kurz #define STM32F746_PG13_FUNC_ETH_MII_TXD0_ETH_RMII_TXD0 0x6d0c
935*797c3c13SMichael Kurz #define STM32F746_PG13_FUNC_FMC_A24 0x6d0d
936*797c3c13SMichael Kurz #define STM32F746_PG13_FUNC_LCD_R0 0x6d0f
937*797c3c13SMichael Kurz #define STM32F746_PG13_FUNC_EVENTOUT 0x6d10
938*797c3c13SMichael Kurz #define STM32F746_PG13_FUNC_ANALOG 0x6d11
939*797c3c13SMichael Kurz 
940*797c3c13SMichael Kurz #define STM32F746_PG14_FUNC_GPIO 0x6e00
941*797c3c13SMichael Kurz #define STM32F746_PG14_FUNC_TRACED1 0x6e01
942*797c3c13SMichael Kurz #define STM32F746_PG14_FUNC_LPTIM1_ETR 0x6e04
943*797c3c13SMichael Kurz #define STM32F746_PG14_FUNC_SPI6_MOSI 0x6e06
944*797c3c13SMichael Kurz #define STM32F746_PG14_FUNC_USART6_TX 0x6e09
945*797c3c13SMichael Kurz #define STM32F746_PG14_FUNC_QUADSPI_BK2_IO3 0x6e0a
946*797c3c13SMichael Kurz #define STM32F746_PG14_FUNC_ETH_MII_TXD1_ETH_RMII_TXD1 0x6e0c
947*797c3c13SMichael Kurz #define STM32F746_PG14_FUNC_FMC_A25 0x6e0d
948*797c3c13SMichael Kurz #define STM32F746_PG14_FUNC_LCD_B0 0x6e0f
949*797c3c13SMichael Kurz #define STM32F746_PG14_FUNC_EVENTOUT 0x6e10
950*797c3c13SMichael Kurz #define STM32F746_PG14_FUNC_ANALOG 0x6e11
951*797c3c13SMichael Kurz 
952*797c3c13SMichael Kurz #define STM32F746_PG15_FUNC_GPIO 0x6f00
953*797c3c13SMichael Kurz #define STM32F746_PG15_FUNC_USART6_CTS 0x6f09
954*797c3c13SMichael Kurz #define STM32F746_PG15_FUNC_FMC_SDNCAS 0x6f0d
955*797c3c13SMichael Kurz #define STM32F746_PG15_FUNC_DCMI_D13 0x6f0e
956*797c3c13SMichael Kurz #define STM32F746_PG15_FUNC_EVENTOUT 0x6f10
957*797c3c13SMichael Kurz #define STM32F746_PG15_FUNC_ANALOG 0x6f11
958*797c3c13SMichael Kurz 
959*797c3c13SMichael Kurz 
960*797c3c13SMichael Kurz #define STM32F746_PH0_FUNC_GPIO 0x7000
961*797c3c13SMichael Kurz #define STM32F746_PH0_FUNC_EVENTOUT 0x7010
962*797c3c13SMichael Kurz #define STM32F746_PH0_FUNC_ANALOG 0x7011
963*797c3c13SMichael Kurz 
964*797c3c13SMichael Kurz #define STM32F746_PH1_FUNC_GPIO 0x7100
965*797c3c13SMichael Kurz #define STM32F746_PH1_FUNC_EVENTOUT 0x7110
966*797c3c13SMichael Kurz #define STM32F746_PH1_FUNC_ANALOG 0x7111
967*797c3c13SMichael Kurz 
968*797c3c13SMichael Kurz #define STM32F746_PH2_FUNC_GPIO 0x7200
969*797c3c13SMichael Kurz #define STM32F746_PH2_FUNC_LPTIM1_IN2 0x7204
970*797c3c13SMichael Kurz #define STM32F746_PH2_FUNC_QUADSPI_BK2_IO0 0x720a
971*797c3c13SMichael Kurz #define STM32F746_PH2_FUNC_SAI2_SCK_B 0x720b
972*797c3c13SMichael Kurz #define STM32F746_PH2_FUNC_ETH_MII_CRS 0x720c
973*797c3c13SMichael Kurz #define STM32F746_PH2_FUNC_FMC_SDCKE0 0x720d
974*797c3c13SMichael Kurz #define STM32F746_PH2_FUNC_LCD_R0 0x720f
975*797c3c13SMichael Kurz #define STM32F746_PH2_FUNC_EVENTOUT 0x7210
976*797c3c13SMichael Kurz #define STM32F746_PH2_FUNC_ANALOG 0x7211
977*797c3c13SMichael Kurz 
978*797c3c13SMichael Kurz #define STM32F746_PH3_FUNC_GPIO 0x7300
979*797c3c13SMichael Kurz #define STM32F746_PH3_FUNC_QUADSPI_BK2_IO1 0x730a
980*797c3c13SMichael Kurz #define STM32F746_PH3_FUNC_SAI2_MCLK_B 0x730b
981*797c3c13SMichael Kurz #define STM32F746_PH3_FUNC_ETH_MII_COL 0x730c
982*797c3c13SMichael Kurz #define STM32F746_PH3_FUNC_FMC_SDNE0 0x730d
983*797c3c13SMichael Kurz #define STM32F746_PH3_FUNC_LCD_R1 0x730f
984*797c3c13SMichael Kurz #define STM32F746_PH3_FUNC_EVENTOUT 0x7310
985*797c3c13SMichael Kurz #define STM32F746_PH3_FUNC_ANALOG 0x7311
986*797c3c13SMichael Kurz 
987*797c3c13SMichael Kurz #define STM32F746_PH4_FUNC_GPIO 0x7400
988*797c3c13SMichael Kurz #define STM32F746_PH4_FUNC_I2C2_SCL 0x7405
989*797c3c13SMichael Kurz #define STM32F746_PH4_FUNC_OTG_HS_ULPI_NXT 0x740b
990*797c3c13SMichael Kurz #define STM32F746_PH4_FUNC_EVENTOUT 0x7410
991*797c3c13SMichael Kurz #define STM32F746_PH4_FUNC_ANALOG 0x7411
992*797c3c13SMichael Kurz 
993*797c3c13SMichael Kurz #define STM32F746_PH5_FUNC_GPIO 0x7500
994*797c3c13SMichael Kurz #define STM32F746_PH5_FUNC_I2C2_SDA 0x7505
995*797c3c13SMichael Kurz #define STM32F746_PH5_FUNC_SPI5_NSS 0x7506
996*797c3c13SMichael Kurz #define STM32F746_PH5_FUNC_FMC_SDNWE 0x750d
997*797c3c13SMichael Kurz #define STM32F746_PH5_FUNC_EVENTOUT 0x7510
998*797c3c13SMichael Kurz #define STM32F746_PH5_FUNC_ANALOG 0x7511
999*797c3c13SMichael Kurz 
1000*797c3c13SMichael Kurz #define STM32F746_PH6_FUNC_GPIO 0x7600
1001*797c3c13SMichael Kurz #define STM32F746_PH6_FUNC_I2C2_SMBA 0x7605
1002*797c3c13SMichael Kurz #define STM32F746_PH6_FUNC_SPI5_SCK 0x7606
1003*797c3c13SMichael Kurz #define STM32F746_PH6_FUNC_TIM12_CH1 0x760a
1004*797c3c13SMichael Kurz #define STM32F746_PH6_FUNC_ETH_MII_RXD2 0x760c
1005*797c3c13SMichael Kurz #define STM32F746_PH6_FUNC_FMC_SDNE1 0x760d
1006*797c3c13SMichael Kurz #define STM32F746_PH6_FUNC_DCMI_D8 0x760e
1007*797c3c13SMichael Kurz #define STM32F746_PH6_FUNC_EVENTOUT 0x7610
1008*797c3c13SMichael Kurz #define STM32F746_PH6_FUNC_ANALOG 0x7611
1009*797c3c13SMichael Kurz 
1010*797c3c13SMichael Kurz #define STM32F746_PH7_FUNC_GPIO 0x7700
1011*797c3c13SMichael Kurz #define STM32F746_PH7_FUNC_I2C3_SCL 0x7705
1012*797c3c13SMichael Kurz #define STM32F746_PH7_FUNC_SPI5_MISO 0x7706
1013*797c3c13SMichael Kurz #define STM32F746_PH7_FUNC_ETH_MII_RXD3 0x770c
1014*797c3c13SMichael Kurz #define STM32F746_PH7_FUNC_FMC_SDCKE1 0x770d
1015*797c3c13SMichael Kurz #define STM32F746_PH7_FUNC_DCMI_D9 0x770e
1016*797c3c13SMichael Kurz #define STM32F746_PH7_FUNC_EVENTOUT 0x7710
1017*797c3c13SMichael Kurz #define STM32F746_PH7_FUNC_ANALOG 0x7711
1018*797c3c13SMichael Kurz 
1019*797c3c13SMichael Kurz #define STM32F746_PH8_FUNC_GPIO 0x7800
1020*797c3c13SMichael Kurz #define STM32F746_PH8_FUNC_I2C3_SDA 0x7805
1021*797c3c13SMichael Kurz #define STM32F746_PH8_FUNC_FMC_D16 0x780d
1022*797c3c13SMichael Kurz #define STM32F746_PH8_FUNC_DCMI_HSYNC 0x780e
1023*797c3c13SMichael Kurz #define STM32F746_PH8_FUNC_LCD_R2 0x780f
1024*797c3c13SMichael Kurz #define STM32F746_PH8_FUNC_EVENTOUT 0x7810
1025*797c3c13SMichael Kurz #define STM32F746_PH8_FUNC_ANALOG 0x7811
1026*797c3c13SMichael Kurz 
1027*797c3c13SMichael Kurz #define STM32F746_PH9_FUNC_GPIO 0x7900
1028*797c3c13SMichael Kurz #define STM32F746_PH9_FUNC_I2C3_SMBA 0x7905
1029*797c3c13SMichael Kurz #define STM32F746_PH9_FUNC_TIM12_CH2 0x790a
1030*797c3c13SMichael Kurz #define STM32F746_PH9_FUNC_FMC_D17 0x790d
1031*797c3c13SMichael Kurz #define STM32F746_PH9_FUNC_DCMI_D0 0x790e
1032*797c3c13SMichael Kurz #define STM32F746_PH9_FUNC_LCD_R3 0x790f
1033*797c3c13SMichael Kurz #define STM32F746_PH9_FUNC_EVENTOUT 0x7910
1034*797c3c13SMichael Kurz #define STM32F746_PH9_FUNC_ANALOG 0x7911
1035*797c3c13SMichael Kurz 
1036*797c3c13SMichael Kurz #define STM32F746_PH10_FUNC_GPIO 0x7a00
1037*797c3c13SMichael Kurz #define STM32F746_PH10_FUNC_TIM5_CH1 0x7a03
1038*797c3c13SMichael Kurz #define STM32F746_PH10_FUNC_I2C4_SMBA 0x7a05
1039*797c3c13SMichael Kurz #define STM32F746_PH10_FUNC_FMC_D18 0x7a0d
1040*797c3c13SMichael Kurz #define STM32F746_PH10_FUNC_DCMI_D1 0x7a0e
1041*797c3c13SMichael Kurz #define STM32F746_PH10_FUNC_LCD_R4 0x7a0f
1042*797c3c13SMichael Kurz #define STM32F746_PH10_FUNC_EVENTOUT 0x7a10
1043*797c3c13SMichael Kurz #define STM32F746_PH10_FUNC_ANALOG 0x7a11
1044*797c3c13SMichael Kurz 
1045*797c3c13SMichael Kurz #define STM32F746_PH11_FUNC_GPIO 0x7b00
1046*797c3c13SMichael Kurz #define STM32F746_PH11_FUNC_TIM5_CH2 0x7b03
1047*797c3c13SMichael Kurz #define STM32F746_PH11_FUNC_I2C4_SCL 0x7b05
1048*797c3c13SMichael Kurz #define STM32F746_PH11_FUNC_FMC_D19 0x7b0d
1049*797c3c13SMichael Kurz #define STM32F746_PH11_FUNC_DCMI_D2 0x7b0e
1050*797c3c13SMichael Kurz #define STM32F746_PH11_FUNC_LCD_R5 0x7b0f
1051*797c3c13SMichael Kurz #define STM32F746_PH11_FUNC_EVENTOUT 0x7b10
1052*797c3c13SMichael Kurz #define STM32F746_PH11_FUNC_ANALOG 0x7b11
1053*797c3c13SMichael Kurz 
1054*797c3c13SMichael Kurz #define STM32F746_PH12_FUNC_GPIO 0x7c00
1055*797c3c13SMichael Kurz #define STM32F746_PH12_FUNC_TIM5_CH3 0x7c03
1056*797c3c13SMichael Kurz #define STM32F746_PH12_FUNC_I2C4_SDA 0x7c05
1057*797c3c13SMichael Kurz #define STM32F746_PH12_FUNC_FMC_D20 0x7c0d
1058*797c3c13SMichael Kurz #define STM32F746_PH12_FUNC_DCMI_D3 0x7c0e
1059*797c3c13SMichael Kurz #define STM32F746_PH12_FUNC_LCD_R6 0x7c0f
1060*797c3c13SMichael Kurz #define STM32F746_PH12_FUNC_EVENTOUT 0x7c10
1061*797c3c13SMichael Kurz #define STM32F746_PH12_FUNC_ANALOG 0x7c11
1062*797c3c13SMichael Kurz 
1063*797c3c13SMichael Kurz #define STM32F746_PH13_FUNC_GPIO 0x7d00
1064*797c3c13SMichael Kurz #define STM32F746_PH13_FUNC_TIM8_CH1N 0x7d04
1065*797c3c13SMichael Kurz #define STM32F746_PH13_FUNC_CAN1_TX 0x7d0a
1066*797c3c13SMichael Kurz #define STM32F746_PH13_FUNC_FMC_D21 0x7d0d
1067*797c3c13SMichael Kurz #define STM32F746_PH13_FUNC_LCD_G2 0x7d0f
1068*797c3c13SMichael Kurz #define STM32F746_PH13_FUNC_EVENTOUT 0x7d10
1069*797c3c13SMichael Kurz #define STM32F746_PH13_FUNC_ANALOG 0x7d11
1070*797c3c13SMichael Kurz 
1071*797c3c13SMichael Kurz #define STM32F746_PH14_FUNC_GPIO 0x7e00
1072*797c3c13SMichael Kurz #define STM32F746_PH14_FUNC_TIM8_CH2N 0x7e04
1073*797c3c13SMichael Kurz #define STM32F746_PH14_FUNC_FMC_D22 0x7e0d
1074*797c3c13SMichael Kurz #define STM32F746_PH14_FUNC_DCMI_D4 0x7e0e
1075*797c3c13SMichael Kurz #define STM32F746_PH14_FUNC_LCD_G3 0x7e0f
1076*797c3c13SMichael Kurz #define STM32F746_PH14_FUNC_EVENTOUT 0x7e10
1077*797c3c13SMichael Kurz #define STM32F746_PH14_FUNC_ANALOG 0x7e11
1078*797c3c13SMichael Kurz 
1079*797c3c13SMichael Kurz #define STM32F746_PH15_FUNC_GPIO 0x7f00
1080*797c3c13SMichael Kurz #define STM32F746_PH15_FUNC_TIM8_CH3N 0x7f04
1081*797c3c13SMichael Kurz #define STM32F746_PH15_FUNC_FMC_D23 0x7f0d
1082*797c3c13SMichael Kurz #define STM32F746_PH15_FUNC_DCMI_D11 0x7f0e
1083*797c3c13SMichael Kurz #define STM32F746_PH15_FUNC_LCD_G4 0x7f0f
1084*797c3c13SMichael Kurz #define STM32F746_PH15_FUNC_EVENTOUT 0x7f10
1085*797c3c13SMichael Kurz #define STM32F746_PH15_FUNC_ANALOG 0x7f11
1086*797c3c13SMichael Kurz 
1087*797c3c13SMichael Kurz 
1088*797c3c13SMichael Kurz #define STM32F746_PI0_FUNC_GPIO 0x8000
1089*797c3c13SMichael Kurz #define STM32F746_PI0_FUNC_TIM5_CH4 0x8003
1090*797c3c13SMichael Kurz #define STM32F746_PI0_FUNC_SPI2_NSS_I2S2_WS 0x8006
1091*797c3c13SMichael Kurz #define STM32F746_PI0_FUNC_FMC_D24 0x800d
1092*797c3c13SMichael Kurz #define STM32F746_PI0_FUNC_DCMI_D13 0x800e
1093*797c3c13SMichael Kurz #define STM32F746_PI0_FUNC_LCD_G5 0x800f
1094*797c3c13SMichael Kurz #define STM32F746_PI0_FUNC_EVENTOUT 0x8010
1095*797c3c13SMichael Kurz #define STM32F746_PI0_FUNC_ANALOG 0x8011
1096*797c3c13SMichael Kurz 
1097*797c3c13SMichael Kurz #define STM32F746_PI1_FUNC_GPIO 0x8100
1098*797c3c13SMichael Kurz #define STM32F746_PI1_FUNC_TIM8_BKIN2 0x8104
1099*797c3c13SMichael Kurz #define STM32F746_PI1_FUNC_SPI2_SCK_I2S2_CK 0x8106
1100*797c3c13SMichael Kurz #define STM32F746_PI1_FUNC_FMC_D25 0x810d
1101*797c3c13SMichael Kurz #define STM32F746_PI1_FUNC_DCMI_D8 0x810e
1102*797c3c13SMichael Kurz #define STM32F746_PI1_FUNC_LCD_G6 0x810f
1103*797c3c13SMichael Kurz #define STM32F746_PI1_FUNC_EVENTOUT 0x8110
1104*797c3c13SMichael Kurz #define STM32F746_PI1_FUNC_ANALOG 0x8111
1105*797c3c13SMichael Kurz 
1106*797c3c13SMichael Kurz #define STM32F746_PI2_FUNC_GPIO 0x8200
1107*797c3c13SMichael Kurz #define STM32F746_PI2_FUNC_TIM8_CH4 0x8204
1108*797c3c13SMichael Kurz #define STM32F746_PI2_FUNC_SPI2_MISO 0x8206
1109*797c3c13SMichael Kurz #define STM32F746_PI2_FUNC_FMC_D26 0x820d
1110*797c3c13SMichael Kurz #define STM32F746_PI2_FUNC_DCMI_D9 0x820e
1111*797c3c13SMichael Kurz #define STM32F746_PI2_FUNC_LCD_G7 0x820f
1112*797c3c13SMichael Kurz #define STM32F746_PI2_FUNC_EVENTOUT 0x8210
1113*797c3c13SMichael Kurz #define STM32F746_PI2_FUNC_ANALOG 0x8211
1114*797c3c13SMichael Kurz 
1115*797c3c13SMichael Kurz #define STM32F746_PI3_FUNC_GPIO 0x8300
1116*797c3c13SMichael Kurz #define STM32F746_PI3_FUNC_TIM8_ETR 0x8304
1117*797c3c13SMichael Kurz #define STM32F746_PI3_FUNC_SPI2_MOSI_I2S2_SD 0x8306
1118*797c3c13SMichael Kurz #define STM32F746_PI3_FUNC_FMC_D27 0x830d
1119*797c3c13SMichael Kurz #define STM32F746_PI3_FUNC_DCMI_D10 0x830e
1120*797c3c13SMichael Kurz #define STM32F746_PI3_FUNC_EVENTOUT 0x8310
1121*797c3c13SMichael Kurz #define STM32F746_PI3_FUNC_ANALOG 0x8311
1122*797c3c13SMichael Kurz 
1123*797c3c13SMichael Kurz #define STM32F746_PI4_FUNC_GPIO 0x8400
1124*797c3c13SMichael Kurz #define STM32F746_PI4_FUNC_TIM8_BKIN 0x8404
1125*797c3c13SMichael Kurz #define STM32F746_PI4_FUNC_SAI2_MCLK_A 0x840b
1126*797c3c13SMichael Kurz #define STM32F746_PI4_FUNC_FMC_NBL2 0x840d
1127*797c3c13SMichael Kurz #define STM32F746_PI4_FUNC_DCMI_D5 0x840e
1128*797c3c13SMichael Kurz #define STM32F746_PI4_FUNC_LCD_B4 0x840f
1129*797c3c13SMichael Kurz #define STM32F746_PI4_FUNC_EVENTOUT 0x8410
1130*797c3c13SMichael Kurz #define STM32F746_PI4_FUNC_ANALOG 0x8411
1131*797c3c13SMichael Kurz 
1132*797c3c13SMichael Kurz #define STM32F746_PI5_FUNC_GPIO 0x8500
1133*797c3c13SMichael Kurz #define STM32F746_PI5_FUNC_TIM8_CH1 0x8504
1134*797c3c13SMichael Kurz #define STM32F746_PI5_FUNC_SAI2_SCK_A 0x850b
1135*797c3c13SMichael Kurz #define STM32F746_PI5_FUNC_FMC_NBL3 0x850d
1136*797c3c13SMichael Kurz #define STM32F746_PI5_FUNC_DCMI_VSYNC 0x850e
1137*797c3c13SMichael Kurz #define STM32F746_PI5_FUNC_LCD_B5 0x850f
1138*797c3c13SMichael Kurz #define STM32F746_PI5_FUNC_EVENTOUT 0x8510
1139*797c3c13SMichael Kurz #define STM32F746_PI5_FUNC_ANALOG 0x8511
1140*797c3c13SMichael Kurz 
1141*797c3c13SMichael Kurz #define STM32F746_PI6_FUNC_GPIO 0x8600
1142*797c3c13SMichael Kurz #define STM32F746_PI6_FUNC_TIM8_CH2 0x8604
1143*797c3c13SMichael Kurz #define STM32F746_PI6_FUNC_SAI2_SD_A 0x860b
1144*797c3c13SMichael Kurz #define STM32F746_PI6_FUNC_FMC_D28 0x860d
1145*797c3c13SMichael Kurz #define STM32F746_PI6_FUNC_DCMI_D6 0x860e
1146*797c3c13SMichael Kurz #define STM32F746_PI6_FUNC_LCD_B6 0x860f
1147*797c3c13SMichael Kurz #define STM32F746_PI6_FUNC_EVENTOUT 0x8610
1148*797c3c13SMichael Kurz #define STM32F746_PI6_FUNC_ANALOG 0x8611
1149*797c3c13SMichael Kurz 
1150*797c3c13SMichael Kurz #define STM32F746_PI7_FUNC_GPIO 0x8700
1151*797c3c13SMichael Kurz #define STM32F746_PI7_FUNC_TIM8_CH3 0x8704
1152*797c3c13SMichael Kurz #define STM32F746_PI7_FUNC_SAI2_FS_A 0x870b
1153*797c3c13SMichael Kurz #define STM32F746_PI7_FUNC_FMC_D29 0x870d
1154*797c3c13SMichael Kurz #define STM32F746_PI7_FUNC_DCMI_D7 0x870e
1155*797c3c13SMichael Kurz #define STM32F746_PI7_FUNC_LCD_B7 0x870f
1156*797c3c13SMichael Kurz #define STM32F746_PI7_FUNC_EVENTOUT 0x8710
1157*797c3c13SMichael Kurz #define STM32F746_PI7_FUNC_ANALOG 0x8711
1158*797c3c13SMichael Kurz 
1159*797c3c13SMichael Kurz #define STM32F746_PI8_FUNC_GPIO 0x8800
1160*797c3c13SMichael Kurz #define STM32F746_PI8_FUNC_EVENTOUT 0x8810
1161*797c3c13SMichael Kurz #define STM32F746_PI8_FUNC_ANALOG 0x8811
1162*797c3c13SMichael Kurz 
1163*797c3c13SMichael Kurz #define STM32F746_PI9_FUNC_GPIO 0x8900
1164*797c3c13SMichael Kurz #define STM32F746_PI9_FUNC_CAN1_RX 0x890a
1165*797c3c13SMichael Kurz #define STM32F746_PI9_FUNC_FMC_D30 0x890d
1166*797c3c13SMichael Kurz #define STM32F746_PI9_FUNC_LCD_VSYNC 0x890f
1167*797c3c13SMichael Kurz #define STM32F746_PI9_FUNC_EVENTOUT 0x8910
1168*797c3c13SMichael Kurz #define STM32F746_PI9_FUNC_ANALOG 0x8911
1169*797c3c13SMichael Kurz 
1170*797c3c13SMichael Kurz #define STM32F746_PI10_FUNC_GPIO 0x8a00
1171*797c3c13SMichael Kurz #define STM32F746_PI10_FUNC_ETH_MII_RX_ER 0x8a0c
1172*797c3c13SMichael Kurz #define STM32F746_PI10_FUNC_FMC_D31 0x8a0d
1173*797c3c13SMichael Kurz #define STM32F746_PI10_FUNC_LCD_HSYNC 0x8a0f
1174*797c3c13SMichael Kurz #define STM32F746_PI10_FUNC_EVENTOUT 0x8a10
1175*797c3c13SMichael Kurz #define STM32F746_PI10_FUNC_ANALOG 0x8a11
1176*797c3c13SMichael Kurz 
1177*797c3c13SMichael Kurz #define STM32F746_PI11_FUNC_GPIO 0x8b00
1178*797c3c13SMichael Kurz #define STM32F746_PI11_FUNC_OTG_HS_ULPI_DIR 0x8b0b
1179*797c3c13SMichael Kurz #define STM32F746_PI11_FUNC_EVENTOUT 0x8b10
1180*797c3c13SMichael Kurz #define STM32F746_PI11_FUNC_ANALOG 0x8b11
1181*797c3c13SMichael Kurz 
1182*797c3c13SMichael Kurz #define STM32F746_PI12_FUNC_GPIO 0x8c00
1183*797c3c13SMichael Kurz #define STM32F746_PI12_FUNC_LCD_HSYNC 0x8c0f
1184*797c3c13SMichael Kurz #define STM32F746_PI12_FUNC_EVENTOUT 0x8c10
1185*797c3c13SMichael Kurz #define STM32F746_PI12_FUNC_ANALOG 0x8c11
1186*797c3c13SMichael Kurz 
1187*797c3c13SMichael Kurz #define STM32F746_PI13_FUNC_GPIO 0x8d00
1188*797c3c13SMichael Kurz #define STM32F746_PI13_FUNC_LCD_VSYNC 0x8d0f
1189*797c3c13SMichael Kurz #define STM32F746_PI13_FUNC_EVENTOUT 0x8d10
1190*797c3c13SMichael Kurz #define STM32F746_PI13_FUNC_ANALOG 0x8d11
1191*797c3c13SMichael Kurz 
1192*797c3c13SMichael Kurz #define STM32F746_PI14_FUNC_GPIO 0x8e00
1193*797c3c13SMichael Kurz #define STM32F746_PI14_FUNC_LCD_CLK 0x8e0f
1194*797c3c13SMichael Kurz #define STM32F746_PI14_FUNC_EVENTOUT 0x8e10
1195*797c3c13SMichael Kurz #define STM32F746_PI14_FUNC_ANALOG 0x8e11
1196*797c3c13SMichael Kurz 
1197*797c3c13SMichael Kurz #define STM32F746_PI15_FUNC_GPIO 0x8f00
1198*797c3c13SMichael Kurz #define STM32F746_PI15_FUNC_LCD_R0 0x8f0f
1199*797c3c13SMichael Kurz #define STM32F746_PI15_FUNC_EVENTOUT 0x8f10
1200*797c3c13SMichael Kurz #define STM32F746_PI15_FUNC_ANALOG 0x8f11
1201*797c3c13SMichael Kurz 
1202*797c3c13SMichael Kurz 
1203*797c3c13SMichael Kurz #define STM32F746_PJ0_FUNC_GPIO 0x9000
1204*797c3c13SMichael Kurz #define STM32F746_PJ0_FUNC_LCD_R1 0x900f
1205*797c3c13SMichael Kurz #define STM32F746_PJ0_FUNC_EVENTOUT 0x9010
1206*797c3c13SMichael Kurz #define STM32F746_PJ0_FUNC_ANALOG 0x9011
1207*797c3c13SMichael Kurz 
1208*797c3c13SMichael Kurz #define STM32F746_PJ1_FUNC_GPIO 0x9100
1209*797c3c13SMichael Kurz #define STM32F746_PJ1_FUNC_LCD_R2 0x910f
1210*797c3c13SMichael Kurz #define STM32F746_PJ1_FUNC_EVENTOUT 0x9110
1211*797c3c13SMichael Kurz #define STM32F746_PJ1_FUNC_ANALOG 0x9111
1212*797c3c13SMichael Kurz 
1213*797c3c13SMichael Kurz #define STM32F746_PJ2_FUNC_GPIO 0x9200
1214*797c3c13SMichael Kurz #define STM32F746_PJ2_FUNC_LCD_R3 0x920f
1215*797c3c13SMichael Kurz #define STM32F746_PJ2_FUNC_EVENTOUT 0x9210
1216*797c3c13SMichael Kurz #define STM32F746_PJ2_FUNC_ANALOG 0x9211
1217*797c3c13SMichael Kurz 
1218*797c3c13SMichael Kurz #define STM32F746_PJ3_FUNC_GPIO 0x9300
1219*797c3c13SMichael Kurz #define STM32F746_PJ3_FUNC_LCD_R4 0x930f
1220*797c3c13SMichael Kurz #define STM32F746_PJ3_FUNC_EVENTOUT 0x9310
1221*797c3c13SMichael Kurz #define STM32F746_PJ3_FUNC_ANALOG 0x9311
1222*797c3c13SMichael Kurz 
1223*797c3c13SMichael Kurz #define STM32F746_PJ4_FUNC_GPIO 0x9400
1224*797c3c13SMichael Kurz #define STM32F746_PJ4_FUNC_LCD_R5 0x940f
1225*797c3c13SMichael Kurz #define STM32F746_PJ4_FUNC_EVENTOUT 0x9410
1226*797c3c13SMichael Kurz #define STM32F746_PJ4_FUNC_ANALOG 0x9411
1227*797c3c13SMichael Kurz 
1228*797c3c13SMichael Kurz #define STM32F746_PJ5_FUNC_GPIO 0x9500
1229*797c3c13SMichael Kurz #define STM32F746_PJ5_FUNC_LCD_R6 0x950f
1230*797c3c13SMichael Kurz #define STM32F746_PJ5_FUNC_EVENTOUT 0x9510
1231*797c3c13SMichael Kurz #define STM32F746_PJ5_FUNC_ANALOG 0x9511
1232*797c3c13SMichael Kurz 
1233*797c3c13SMichael Kurz #define STM32F746_PJ6_FUNC_GPIO 0x9600
1234*797c3c13SMichael Kurz #define STM32F746_PJ6_FUNC_LCD_R7 0x960f
1235*797c3c13SMichael Kurz #define STM32F746_PJ6_FUNC_EVENTOUT 0x9610
1236*797c3c13SMichael Kurz #define STM32F746_PJ6_FUNC_ANALOG 0x9611
1237*797c3c13SMichael Kurz 
1238*797c3c13SMichael Kurz #define STM32F746_PJ7_FUNC_GPIO 0x9700
1239*797c3c13SMichael Kurz #define STM32F746_PJ7_FUNC_LCD_G0 0x970f
1240*797c3c13SMichael Kurz #define STM32F746_PJ7_FUNC_EVENTOUT 0x9710
1241*797c3c13SMichael Kurz #define STM32F746_PJ7_FUNC_ANALOG 0x9711
1242*797c3c13SMichael Kurz 
1243*797c3c13SMichael Kurz #define STM32F746_PJ8_FUNC_GPIO 0x9800
1244*797c3c13SMichael Kurz #define STM32F746_PJ8_FUNC_LCD_G1 0x980f
1245*797c3c13SMichael Kurz #define STM32F746_PJ8_FUNC_EVENTOUT 0x9810
1246*797c3c13SMichael Kurz #define STM32F746_PJ8_FUNC_ANALOG 0x9811
1247*797c3c13SMichael Kurz 
1248*797c3c13SMichael Kurz #define STM32F746_PJ9_FUNC_GPIO 0x9900
1249*797c3c13SMichael Kurz #define STM32F746_PJ9_FUNC_LCD_G2 0x990f
1250*797c3c13SMichael Kurz #define STM32F746_PJ9_FUNC_EVENTOUT 0x9910
1251*797c3c13SMichael Kurz #define STM32F746_PJ9_FUNC_ANALOG 0x9911
1252*797c3c13SMichael Kurz 
1253*797c3c13SMichael Kurz #define STM32F746_PJ10_FUNC_GPIO 0x9a00
1254*797c3c13SMichael Kurz #define STM32F746_PJ10_FUNC_LCD_G3 0x9a0f
1255*797c3c13SMichael Kurz #define STM32F746_PJ10_FUNC_EVENTOUT 0x9a10
1256*797c3c13SMichael Kurz #define STM32F746_PJ10_FUNC_ANALOG 0x9a11
1257*797c3c13SMichael Kurz 
1258*797c3c13SMichael Kurz #define STM32F746_PJ11_FUNC_GPIO 0x9b00
1259*797c3c13SMichael Kurz #define STM32F746_PJ11_FUNC_LCD_G4 0x9b0f
1260*797c3c13SMichael Kurz #define STM32F746_PJ11_FUNC_EVENTOUT 0x9b10
1261*797c3c13SMichael Kurz #define STM32F746_PJ11_FUNC_ANALOG 0x9b11
1262*797c3c13SMichael Kurz 
1263*797c3c13SMichael Kurz #define STM32F746_PJ12_FUNC_GPIO 0x9c00
1264*797c3c13SMichael Kurz #define STM32F746_PJ12_FUNC_LCD_B0 0x9c0f
1265*797c3c13SMichael Kurz #define STM32F746_PJ12_FUNC_EVENTOUT 0x9c10
1266*797c3c13SMichael Kurz #define STM32F746_PJ12_FUNC_ANALOG 0x9c11
1267*797c3c13SMichael Kurz 
1268*797c3c13SMichael Kurz #define STM32F746_PJ13_FUNC_GPIO 0x9d00
1269*797c3c13SMichael Kurz #define STM32F746_PJ13_FUNC_LCD_B1 0x9d0f
1270*797c3c13SMichael Kurz #define STM32F746_PJ13_FUNC_EVENTOUT 0x9d10
1271*797c3c13SMichael Kurz #define STM32F746_PJ13_FUNC_ANALOG 0x9d11
1272*797c3c13SMichael Kurz 
1273*797c3c13SMichael Kurz #define STM32F746_PJ14_FUNC_GPIO 0x9e00
1274*797c3c13SMichael Kurz #define STM32F746_PJ14_FUNC_LCD_B2 0x9e0f
1275*797c3c13SMichael Kurz #define STM32F746_PJ14_FUNC_EVENTOUT 0x9e10
1276*797c3c13SMichael Kurz #define STM32F746_PJ14_FUNC_ANALOG 0x9e11
1277*797c3c13SMichael Kurz 
1278*797c3c13SMichael Kurz #define STM32F746_PJ15_FUNC_GPIO 0x9f00
1279*797c3c13SMichael Kurz #define STM32F746_PJ15_FUNC_LCD_B3 0x9f0f
1280*797c3c13SMichael Kurz #define STM32F746_PJ15_FUNC_EVENTOUT 0x9f10
1281*797c3c13SMichael Kurz #define STM32F746_PJ15_FUNC_ANALOG 0x9f11
1282*797c3c13SMichael Kurz 
1283*797c3c13SMichael Kurz 
1284*797c3c13SMichael Kurz #define STM32F746_PK0_FUNC_GPIO 0xa000
1285*797c3c13SMichael Kurz #define STM32F746_PK0_FUNC_LCD_G5 0xa00f
1286*797c3c13SMichael Kurz #define STM32F746_PK0_FUNC_EVENTOUT 0xa010
1287*797c3c13SMichael Kurz #define STM32F746_PK0_FUNC_ANALOG 0xa011
1288*797c3c13SMichael Kurz 
1289*797c3c13SMichael Kurz #define STM32F746_PK1_FUNC_GPIO 0xa100
1290*797c3c13SMichael Kurz #define STM32F746_PK1_FUNC_LCD_G6 0xa10f
1291*797c3c13SMichael Kurz #define STM32F746_PK1_FUNC_EVENTOUT 0xa110
1292*797c3c13SMichael Kurz #define STM32F746_PK1_FUNC_ANALOG 0xa111
1293*797c3c13SMichael Kurz 
1294*797c3c13SMichael Kurz #define STM32F746_PK2_FUNC_GPIO 0xa200
1295*797c3c13SMichael Kurz #define STM32F746_PK2_FUNC_LCD_G7 0xa20f
1296*797c3c13SMichael Kurz #define STM32F746_PK2_FUNC_EVENTOUT 0xa210
1297*797c3c13SMichael Kurz #define STM32F746_PK2_FUNC_ANALOG 0xa211
1298*797c3c13SMichael Kurz 
1299*797c3c13SMichael Kurz #define STM32F746_PK3_FUNC_GPIO 0xa300
1300*797c3c13SMichael Kurz #define STM32F746_PK3_FUNC_LCD_B4 0xa30f
1301*797c3c13SMichael Kurz #define STM32F746_PK3_FUNC_EVENTOUT 0xa310
1302*797c3c13SMichael Kurz #define STM32F746_PK3_FUNC_ANALOG 0xa311
1303*797c3c13SMichael Kurz 
1304*797c3c13SMichael Kurz #define STM32F746_PK4_FUNC_GPIO 0xa400
1305*797c3c13SMichael Kurz #define STM32F746_PK4_FUNC_LCD_B5 0xa40f
1306*797c3c13SMichael Kurz #define STM32F746_PK4_FUNC_EVENTOUT 0xa410
1307*797c3c13SMichael Kurz #define STM32F746_PK4_FUNC_ANALOG 0xa411
1308*797c3c13SMichael Kurz 
1309*797c3c13SMichael Kurz #define STM32F746_PK5_FUNC_GPIO 0xa500
1310*797c3c13SMichael Kurz #define STM32F746_PK5_FUNC_LCD_B6 0xa50f
1311*797c3c13SMichael Kurz #define STM32F746_PK5_FUNC_EVENTOUT 0xa510
1312*797c3c13SMichael Kurz #define STM32F746_PK5_FUNC_ANALOG 0xa511
1313*797c3c13SMichael Kurz 
1314*797c3c13SMichael Kurz #define STM32F746_PK6_FUNC_GPIO 0xa600
1315*797c3c13SMichael Kurz #define STM32F746_PK6_FUNC_LCD_B7 0xa60f
1316*797c3c13SMichael Kurz #define STM32F746_PK6_FUNC_EVENTOUT 0xa610
1317*797c3c13SMichael Kurz #define STM32F746_PK6_FUNC_ANALOG 0xa611
1318*797c3c13SMichael Kurz 
1319*797c3c13SMichael Kurz #define STM32F746_PK7_FUNC_GPIO 0xa700
1320*797c3c13SMichael Kurz #define STM32F746_PK7_FUNC_LCD_DE 0xa70f
1321*797c3c13SMichael Kurz #define STM32F746_PK7_FUNC_EVENTOUT 0xa710
1322*797c3c13SMichael Kurz #define STM32F746_PK7_FUNC_ANALOG 0xa711
1323*797c3c13SMichael Kurz 
1324*797c3c13SMichael Kurz #endif /* _DT_BINDINGS_STM32F746_PINFUNC_H */
1325