1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0 */ 2754204b5SSimon Glass /* 3754204b5SSimon Glass * This header provides constants for Tegra pinctrl bindings. 4754204b5SSimon Glass * 5754204b5SSimon Glass * Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved. 6754204b5SSimon Glass * 7754204b5SSimon Glass * Author: Laxman Dewangan <ldewangan@nvidia.com> 8754204b5SSimon Glass */ 9754204b5SSimon Glass 10754204b5SSimon Glass #ifndef _DT_BINDINGS_PINCTRL_TEGRA_H 11754204b5SSimon Glass #define _DT_BINDINGS_PINCTRL_TEGRA_H 12754204b5SSimon Glass 13754204b5SSimon Glass /* 14754204b5SSimon Glass * Enable/disable for diffeent dt properties. This is applicable for 15754204b5SSimon Glass * properties nvidia,enable-input, nvidia,tristate, nvidia,open-drain, 16754204b5SSimon Glass * nvidia,lock, nvidia,rcv-sel, nvidia,high-speed-mode, nvidia,schmitt. 17754204b5SSimon Glass */ 18754204b5SSimon Glass #define TEGRA_PIN_DISABLE 0 19754204b5SSimon Glass #define TEGRA_PIN_ENABLE 1 20754204b5SSimon Glass 21754204b5SSimon Glass #define TEGRA_PIN_PULL_NONE 0 22754204b5SSimon Glass #define TEGRA_PIN_PULL_DOWN 1 23754204b5SSimon Glass #define TEGRA_PIN_PULL_UP 2 24754204b5SSimon Glass 25754204b5SSimon Glass /* Low power mode driver */ 26754204b5SSimon Glass #define TEGRA_PIN_LP_DRIVE_DIV_8 0 27754204b5SSimon Glass #define TEGRA_PIN_LP_DRIVE_DIV_4 1 28754204b5SSimon Glass #define TEGRA_PIN_LP_DRIVE_DIV_2 2 29754204b5SSimon Glass #define TEGRA_PIN_LP_DRIVE_DIV_1 3 30754204b5SSimon Glass 31754204b5SSimon Glass /* Rising/Falling slew rate */ 32754204b5SSimon Glass #define TEGRA_PIN_SLEW_RATE_FASTEST 0 33754204b5SSimon Glass #define TEGRA_PIN_SLEW_RATE_FAST 1 34754204b5SSimon Glass #define TEGRA_PIN_SLEW_RATE_SLOW 2 35754204b5SSimon Glass #define TEGRA_PIN_SLEW_RATE_SLOWEST 3 36754204b5SSimon Glass 37754204b5SSimon Glass #endif 38