1*46b1e54bSPatrice Chotard /* SPDX-License-Identifier: GPL-2.0 */ 2*46b1e54bSPatrice Chotard /* 3*46b1e54bSPatrice Chotard * This header provides constants for the STM32F4 RCC IP 4*46b1e54bSPatrice Chotard */ 5*46b1e54bSPatrice Chotard 6*46b1e54bSPatrice Chotard #ifndef _DT_BINDINGS_MFD_STM32F4_RCC_H 7*46b1e54bSPatrice Chotard #define _DT_BINDINGS_MFD_STM32F4_RCC_H 8*46b1e54bSPatrice Chotard 9*46b1e54bSPatrice Chotard /* AHB1 */ 10*46b1e54bSPatrice Chotard #define STM32F4_RCC_AHB1_GPIOA 0 11*46b1e54bSPatrice Chotard #define STM32F4_RCC_AHB1_GPIOB 1 12*46b1e54bSPatrice Chotard #define STM32F4_RCC_AHB1_GPIOC 2 13*46b1e54bSPatrice Chotard #define STM32F4_RCC_AHB1_GPIOD 3 14*46b1e54bSPatrice Chotard #define STM32F4_RCC_AHB1_GPIOE 4 15*46b1e54bSPatrice Chotard #define STM32F4_RCC_AHB1_GPIOF 5 16*46b1e54bSPatrice Chotard #define STM32F4_RCC_AHB1_GPIOG 6 17*46b1e54bSPatrice Chotard #define STM32F4_RCC_AHB1_GPIOH 7 18*46b1e54bSPatrice Chotard #define STM32F4_RCC_AHB1_GPIOI 8 19*46b1e54bSPatrice Chotard #define STM32F4_RCC_AHB1_GPIOJ 9 20*46b1e54bSPatrice Chotard #define STM32F4_RCC_AHB1_GPIOK 10 21*46b1e54bSPatrice Chotard #define STM32F4_RCC_AHB1_CRC 12 22*46b1e54bSPatrice Chotard #define STM32F4_RCC_AHB1_BKPSRAM 18 23*46b1e54bSPatrice Chotard #define STM32F4_RCC_AHB1_CCMDATARAM 20 24*46b1e54bSPatrice Chotard #define STM32F4_RCC_AHB1_DMA1 21 25*46b1e54bSPatrice Chotard #define STM32F4_RCC_AHB1_DMA2 22 26*46b1e54bSPatrice Chotard #define STM32F4_RCC_AHB1_DMA2D 23 27*46b1e54bSPatrice Chotard #define STM32F4_RCC_AHB1_ETHMAC 25 28*46b1e54bSPatrice Chotard #define STM32F4_RCC_AHB1_ETHMACTX 26 29*46b1e54bSPatrice Chotard #define STM32F4_RCC_AHB1_ETHMACRX 27 30*46b1e54bSPatrice Chotard #define STM32F4_RCC_AHB1_ETHMACPTP 28 31*46b1e54bSPatrice Chotard #define STM32F4_RCC_AHB1_OTGHS 29 32*46b1e54bSPatrice Chotard #define STM32F4_RCC_AHB1_OTGHSULPI 30 33*46b1e54bSPatrice Chotard 34*46b1e54bSPatrice Chotard #define STM32F4_AHB1_RESET(bit) (STM32F4_RCC_AHB1_##bit + (0x10 * 8)) 35*46b1e54bSPatrice Chotard #define STM32F4_AHB1_CLOCK(bit) (STM32F4_RCC_AHB1_##bit) 36*46b1e54bSPatrice Chotard 37*46b1e54bSPatrice Chotard /* AHB2 */ 38*46b1e54bSPatrice Chotard #define STM32F4_RCC_AHB2_DCMI 0 39*46b1e54bSPatrice Chotard #define STM32F4_RCC_AHB2_CRYP 4 40*46b1e54bSPatrice Chotard #define STM32F4_RCC_AHB2_HASH 5 41*46b1e54bSPatrice Chotard #define STM32F4_RCC_AHB2_RNG 6 42*46b1e54bSPatrice Chotard #define STM32F4_RCC_AHB2_OTGFS 7 43*46b1e54bSPatrice Chotard 44*46b1e54bSPatrice Chotard #define STM32F4_AHB2_RESET(bit) (STM32F4_RCC_AHB2_##bit + (0x14 * 8)) 45*46b1e54bSPatrice Chotard #define STM32F4_AHB2_CLOCK(bit) (STM32F4_RCC_AHB2_##bit + 0x20) 46*46b1e54bSPatrice Chotard 47*46b1e54bSPatrice Chotard /* AHB3 */ 48*46b1e54bSPatrice Chotard #define STM32F4_RCC_AHB3_FMC 0 49*46b1e54bSPatrice Chotard #define STM32F4_RCC_AHB3_QSPI 1 50*46b1e54bSPatrice Chotard 51*46b1e54bSPatrice Chotard #define STM32F4_AHB3_RESET(bit) (STM32F4_RCC_AHB3_##bit + (0x18 * 8)) 52*46b1e54bSPatrice Chotard #define STM32F4_AHB3_CLOCK(bit) (STM32F4_RCC_AHB3_##bit + 0x40) 53*46b1e54bSPatrice Chotard 54*46b1e54bSPatrice Chotard /* APB1 */ 55*46b1e54bSPatrice Chotard #define STM32F4_RCC_APB1_TIM2 0 56*46b1e54bSPatrice Chotard #define STM32F4_RCC_APB1_TIM3 1 57*46b1e54bSPatrice Chotard #define STM32F4_RCC_APB1_TIM4 2 58*46b1e54bSPatrice Chotard #define STM32F4_RCC_APB1_TIM5 3 59*46b1e54bSPatrice Chotard #define STM32F4_RCC_APB1_TIM6 4 60*46b1e54bSPatrice Chotard #define STM32F4_RCC_APB1_TIM7 5 61*46b1e54bSPatrice Chotard #define STM32F4_RCC_APB1_TIM12 6 62*46b1e54bSPatrice Chotard #define STM32F4_RCC_APB1_TIM13 7 63*46b1e54bSPatrice Chotard #define STM32F4_RCC_APB1_TIM14 8 64*46b1e54bSPatrice Chotard #define STM32F4_RCC_APB1_WWDG 11 65*46b1e54bSPatrice Chotard #define STM32F4_RCC_APB1_SPI2 14 66*46b1e54bSPatrice Chotard #define STM32F4_RCC_APB1_SPI3 15 67*46b1e54bSPatrice Chotard #define STM32F4_RCC_APB1_UART2 17 68*46b1e54bSPatrice Chotard #define STM32F4_RCC_APB1_UART3 18 69*46b1e54bSPatrice Chotard #define STM32F4_RCC_APB1_UART4 19 70*46b1e54bSPatrice Chotard #define STM32F4_RCC_APB1_UART5 20 71*46b1e54bSPatrice Chotard #define STM32F4_RCC_APB1_I2C1 21 72*46b1e54bSPatrice Chotard #define STM32F4_RCC_APB1_I2C2 22 73*46b1e54bSPatrice Chotard #define STM32F4_RCC_APB1_I2C3 23 74*46b1e54bSPatrice Chotard #define STM32F4_RCC_APB1_CAN1 25 75*46b1e54bSPatrice Chotard #define STM32F4_RCC_APB1_CAN2 26 76*46b1e54bSPatrice Chotard #define STM32F4_RCC_APB1_PWR 28 77*46b1e54bSPatrice Chotard #define STM32F4_RCC_APB1_DAC 29 78*46b1e54bSPatrice Chotard #define STM32F4_RCC_APB1_UART7 30 79*46b1e54bSPatrice Chotard #define STM32F4_RCC_APB1_UART8 31 80*46b1e54bSPatrice Chotard 81*46b1e54bSPatrice Chotard #define STM32F4_APB1_RESET(bit) (STM32F4_RCC_APB1_##bit + (0x20 * 8)) 82*46b1e54bSPatrice Chotard #define STM32F4_APB1_CLOCK(bit) (STM32F4_RCC_APB1_##bit + 0x80) 83*46b1e54bSPatrice Chotard 84*46b1e54bSPatrice Chotard /* APB2 */ 85*46b1e54bSPatrice Chotard #define STM32F4_RCC_APB2_TIM1 0 86*46b1e54bSPatrice Chotard #define STM32F4_RCC_APB2_TIM8 1 87*46b1e54bSPatrice Chotard #define STM32F4_RCC_APB2_USART1 4 88*46b1e54bSPatrice Chotard #define STM32F4_RCC_APB2_USART6 5 89*46b1e54bSPatrice Chotard #define STM32F4_RCC_APB2_ADC1 8 90*46b1e54bSPatrice Chotard #define STM32F4_RCC_APB2_ADC2 9 91*46b1e54bSPatrice Chotard #define STM32F4_RCC_APB2_ADC3 10 92*46b1e54bSPatrice Chotard #define STM32F4_RCC_APB2_SDIO 11 93*46b1e54bSPatrice Chotard #define STM32F4_RCC_APB2_SPI1 12 94*46b1e54bSPatrice Chotard #define STM32F4_RCC_APB2_SPI4 13 95*46b1e54bSPatrice Chotard #define STM32F4_RCC_APB2_SYSCFG 14 96*46b1e54bSPatrice Chotard #define STM32F4_RCC_APB2_TIM9 16 97*46b1e54bSPatrice Chotard #define STM32F4_RCC_APB2_TIM10 17 98*46b1e54bSPatrice Chotard #define STM32F4_RCC_APB2_TIM11 18 99*46b1e54bSPatrice Chotard #define STM32F4_RCC_APB2_SPI5 20 100*46b1e54bSPatrice Chotard #define STM32F4_RCC_APB2_SPI6 21 101*46b1e54bSPatrice Chotard #define STM32F4_RCC_APB2_SAI1 22 102*46b1e54bSPatrice Chotard #define STM32F4_RCC_APB2_LTDC 26 103*46b1e54bSPatrice Chotard #define STM32F4_RCC_APB2_DSI 27 104*46b1e54bSPatrice Chotard 105*46b1e54bSPatrice Chotard #define STM32F4_APB2_RESET(bit) (STM32F4_RCC_APB2_##bit + (0x24 * 8)) 106*46b1e54bSPatrice Chotard #define STM32F4_APB2_CLOCK(bit) (STM32F4_RCC_APB2_##bit + 0xA0) 107*46b1e54bSPatrice Chotard 108*46b1e54bSPatrice Chotard #endif /* _DT_BINDINGS_MFD_STM32F4_RCC_H */ 109