1*5c31e7abSStephen Warren #ifndef DT_BINDINGS_MEMORY_TEGRA114_MC_H 2*5c31e7abSStephen Warren #define DT_BINDINGS_MEMORY_TEGRA114_MC_H 3*5c31e7abSStephen Warren 4*5c31e7abSStephen Warren #define TEGRA_SWGROUP_PTC 0 5*5c31e7abSStephen Warren #define TEGRA_SWGROUP_DC 1 6*5c31e7abSStephen Warren #define TEGRA_SWGROUP_DCB 2 7*5c31e7abSStephen Warren #define TEGRA_SWGROUP_EPP 3 8*5c31e7abSStephen Warren #define TEGRA_SWGROUP_G2 4 9*5c31e7abSStephen Warren #define TEGRA_SWGROUP_AVPC 5 10*5c31e7abSStephen Warren #define TEGRA_SWGROUP_NV 6 11*5c31e7abSStephen Warren #define TEGRA_SWGROUP_HDA 7 12*5c31e7abSStephen Warren #define TEGRA_SWGROUP_HC 8 13*5c31e7abSStephen Warren #define TEGRA_SWGROUP_MSENC 9 14*5c31e7abSStephen Warren #define TEGRA_SWGROUP_PPCS 10 15*5c31e7abSStephen Warren #define TEGRA_SWGROUP_VDE 11 16*5c31e7abSStephen Warren #define TEGRA_SWGROUP_MPCORELP 12 17*5c31e7abSStephen Warren #define TEGRA_SWGROUP_MPCORE 13 18*5c31e7abSStephen Warren #define TEGRA_SWGROUP_VI 14 19*5c31e7abSStephen Warren #define TEGRA_SWGROUP_ISP 15 20*5c31e7abSStephen Warren #define TEGRA_SWGROUP_XUSB_HOST 16 21*5c31e7abSStephen Warren #define TEGRA_SWGROUP_XUSB_DEV 17 22*5c31e7abSStephen Warren #define TEGRA_SWGROUP_EMUCIF 18 23*5c31e7abSStephen Warren #define TEGRA_SWGROUP_TSEC 19 24*5c31e7abSStephen Warren 25*5c31e7abSStephen Warren #endif 26