15318f18dSGabriel Huau /* 25318f18dSGabriel Huau * This header provides constants for binding intel,x86-pinctrl. 35318f18dSGabriel Huau */ 45318f18dSGabriel Huau 55318f18dSGabriel Huau #ifndef _DT_BINDINGS_GPIO_X86_GPIO_H 65318f18dSGabriel Huau #define _DT_BINDINGS_GPIO_X86_GPIO_H 75318f18dSGabriel Huau 85318f18dSGabriel Huau #include <dt-bindings/gpio/gpio.h> 95318f18dSGabriel Huau 105318f18dSGabriel Huau #define GPIO_MODE_NATIVE 0 115318f18dSGabriel Huau #define GPIO_MODE_GPIO 1 125318f18dSGabriel Huau 135318f18dSGabriel Huau #define GPIO_MODE_FUNC0 0 145318f18dSGabriel Huau #define GPIO_MODE_FUNC1 1 155318f18dSGabriel Huau #define GPIO_MODE_FUNC2 2 165318f18dSGabriel Huau #define GPIO_MODE_FUNC3 3 175318f18dSGabriel Huau #define GPIO_MODE_FUNC4 4 185318f18dSGabriel Huau #define GPIO_MODE_FUNC5 5 195318f18dSGabriel Huau #define GPIO_MODE_FUNC6 6 205318f18dSGabriel Huau 215318f18dSGabriel Huau #define PIN_INPUT 0 225318f18dSGabriel Huau #define PIN_OUTPUT 1 235318f18dSGabriel Huau 245318f18dSGabriel Huau #define PIN_INPUT_NOPULL 0 255318f18dSGabriel Huau #define PIN_INPUT_PULLUP 1 265318f18dSGabriel Huau #define PIN_INPUT_PULLDOWN 2 275318f18dSGabriel Huau 285318f18dSGabriel Huau #define PULL_STR_2K 0 295318f18dSGabriel Huau #define PULL_STR_20K 2 305318f18dSGabriel Huau 31*b24f5c4fSSimon Glass #define ROUTE_SCI 0 32*b24f5c4fSSimon Glass #define ROUTE_SMI 1 33*b24f5c4fSSimon Glass 34*b24f5c4fSSimon Glass #define OWNER_ACPI 0 35*b24f5c4fSSimon Glass #define OWNER_GPIO 1 36*b24f5c4fSSimon Glass 37*b24f5c4fSSimon Glass #define PIRQ_APIC_MASK 0 38*b24f5c4fSSimon Glass #define PIRQ_APIC_ROUTE 1 39*b24f5c4fSSimon Glass 40*b24f5c4fSSimon Glass #define TRIGGER_EDGE 0 41*b24f5c4fSSimon Glass #define TRIGGER_LEVEL 1 42*b24f5c4fSSimon Glass 435318f18dSGabriel Huau #endif 44