1*c3691392SSimon Glass /* 2*c3691392SSimon Glass * This header provides constants for binding nvidia,tegra30-car. 3*c3691392SSimon Glass * 4*c3691392SSimon Glass * The first 130 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB 5*c3691392SSimon Glass * registers. These IDs often match those in the CAR's RST_DEVICES registers, 6*c3691392SSimon Glass * but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In 7*c3691392SSimon Glass * this case, those clocks are assigned IDs above 160 in order to highlight 8*c3691392SSimon Glass * this issue. Implementations that interpret these clock IDs as bit values 9*c3691392SSimon Glass * within the CLK_OUT_ENB or RST_DEVICES registers should be careful to 10*c3691392SSimon Glass * explicitly handle these special cases. 11*c3691392SSimon Glass * 12*c3691392SSimon Glass * The balance of the clocks controlled by the CAR are assigned IDs of 160 and 13*c3691392SSimon Glass * above. 14*c3691392SSimon Glass */ 15*c3691392SSimon Glass 16*c3691392SSimon Glass #ifndef _DT_BINDINGS_CLOCK_TEGRA30_CAR_H 17*c3691392SSimon Glass #define _DT_BINDINGS_CLOCK_TEGRA30_CAR_H 18*c3691392SSimon Glass 19*c3691392SSimon Glass #define TEGRA30_CLK_CPU 0 20*c3691392SSimon Glass /* 1 */ 21*c3691392SSimon Glass /* 2 */ 22*c3691392SSimon Glass /* 3 */ 23*c3691392SSimon Glass #define TEGRA30_CLK_RTC 4 24*c3691392SSimon Glass #define TEGRA30_CLK_TIMER 5 25*c3691392SSimon Glass #define TEGRA30_CLK_UARTA 6 26*c3691392SSimon Glass /* 7 (register bit affects uartb and vfir) */ 27*c3691392SSimon Glass #define TEGRA30_CLK_GPIO 8 28*c3691392SSimon Glass #define TEGRA30_CLK_SDMMC2 9 29*c3691392SSimon Glass /* 10 (register bit affects spdif_in and spdif_out) */ 30*c3691392SSimon Glass #define TEGRA30_CLK_I2S1 11 31*c3691392SSimon Glass #define TEGRA30_CLK_I2C1 12 32*c3691392SSimon Glass #define TEGRA30_CLK_NDFLASH 13 33*c3691392SSimon Glass #define TEGRA30_CLK_SDMMC1 14 34*c3691392SSimon Glass #define TEGRA30_CLK_SDMMC4 15 35*c3691392SSimon Glass /* 16 */ 36*c3691392SSimon Glass #define TEGRA30_CLK_PWM 17 37*c3691392SSimon Glass #define TEGRA30_CLK_I2S2 18 38*c3691392SSimon Glass #define TEGRA30_CLK_EPP 19 39*c3691392SSimon Glass /* 20 (register bit affects vi and vi_sensor) */ 40*c3691392SSimon Glass #define TEGRA30_CLK_GR2D 21 41*c3691392SSimon Glass #define TEGRA30_CLK_USBD 22 42*c3691392SSimon Glass #define TEGRA30_CLK_ISP 23 43*c3691392SSimon Glass #define TEGRA30_CLK_GR3D 24 44*c3691392SSimon Glass /* 25 */ 45*c3691392SSimon Glass #define TEGRA30_CLK_DISP2 26 46*c3691392SSimon Glass #define TEGRA30_CLK_DISP1 27 47*c3691392SSimon Glass #define TEGRA30_CLK_HOST1X 28 48*c3691392SSimon Glass #define TEGRA30_CLK_VCP 29 49*c3691392SSimon Glass #define TEGRA30_CLK_I2S0 30 50*c3691392SSimon Glass #define TEGRA30_CLK_COP_CACHE 31 51*c3691392SSimon Glass 52*c3691392SSimon Glass #define TEGRA30_CLK_MC 32 53*c3691392SSimon Glass #define TEGRA30_CLK_AHBDMA 33 54*c3691392SSimon Glass #define TEGRA30_CLK_APBDMA 34 55*c3691392SSimon Glass /* 35 */ 56*c3691392SSimon Glass #define TEGRA30_CLK_KBC 36 57*c3691392SSimon Glass #define TEGRA30_CLK_STATMON 37 58*c3691392SSimon Glass #define TEGRA30_CLK_PMC 38 59*c3691392SSimon Glass /* 39 (register bit affects fuse and fuse_burn) */ 60*c3691392SSimon Glass #define TEGRA30_CLK_KFUSE 40 61*c3691392SSimon Glass #define TEGRA30_CLK_SBC1 41 62*c3691392SSimon Glass #define TEGRA30_CLK_NOR 42 63*c3691392SSimon Glass /* 43 */ 64*c3691392SSimon Glass #define TEGRA30_CLK_SBC2 44 65*c3691392SSimon Glass /* 45 */ 66*c3691392SSimon Glass #define TEGRA30_CLK_SBC3 46 67*c3691392SSimon Glass #define TEGRA30_CLK_I2C5 47 68*c3691392SSimon Glass #define TEGRA30_CLK_DSIA 48 69*c3691392SSimon Glass /* 49 (register bit affects cve and tvo) */ 70*c3691392SSimon Glass #define TEGRA30_CLK_MIPI 50 71*c3691392SSimon Glass #define TEGRA30_CLK_HDMI 51 72*c3691392SSimon Glass #define TEGRA30_CLK_CSI 52 73*c3691392SSimon Glass #define TEGRA30_CLK_TVDAC 53 74*c3691392SSimon Glass #define TEGRA30_CLK_I2C2 54 75*c3691392SSimon Glass #define TEGRA30_CLK_UARTC 55 76*c3691392SSimon Glass /* 56 */ 77*c3691392SSimon Glass #define TEGRA30_CLK_EMC 57 78*c3691392SSimon Glass #define TEGRA30_CLK_USB2 58 79*c3691392SSimon Glass #define TEGRA30_CLK_USB3 59 80*c3691392SSimon Glass #define TEGRA30_CLK_MPE 60 81*c3691392SSimon Glass #define TEGRA30_CLK_VDE 61 82*c3691392SSimon Glass #define TEGRA30_CLK_BSEA 62 83*c3691392SSimon Glass #define TEGRA30_CLK_BSEV 63 84*c3691392SSimon Glass 85*c3691392SSimon Glass #define TEGRA30_CLK_SPEEDO 64 86*c3691392SSimon Glass #define TEGRA30_CLK_UARTD 65 87*c3691392SSimon Glass #define TEGRA30_CLK_UARTE 66 88*c3691392SSimon Glass #define TEGRA30_CLK_I2C3 67 89*c3691392SSimon Glass #define TEGRA30_CLK_SBC4 68 90*c3691392SSimon Glass #define TEGRA30_CLK_SDMMC3 69 91*c3691392SSimon Glass #define TEGRA30_CLK_PCIE 70 92*c3691392SSimon Glass #define TEGRA30_CLK_OWR 71 93*c3691392SSimon Glass #define TEGRA30_CLK_AFI 72 94*c3691392SSimon Glass #define TEGRA30_CLK_CSITE 73 95*c3691392SSimon Glass /* 74 */ 96*c3691392SSimon Glass #define TEGRA30_CLK_AVPUCQ 75 97*c3691392SSimon Glass #define TEGRA30_CLK_LA 76 98*c3691392SSimon Glass /* 77 */ 99*c3691392SSimon Glass /* 78 */ 100*c3691392SSimon Glass #define TEGRA30_CLK_DTV 79 101*c3691392SSimon Glass #define TEGRA30_CLK_NDSPEED 80 102*c3691392SSimon Glass #define TEGRA30_CLK_I2CSLOW 81 103*c3691392SSimon Glass #define TEGRA30_CLK_DSIB 82 104*c3691392SSimon Glass /* 83 */ 105*c3691392SSimon Glass #define TEGRA30_CLK_IRAMA 84 106*c3691392SSimon Glass #define TEGRA30_CLK_IRAMB 85 107*c3691392SSimon Glass #define TEGRA30_CLK_IRAMC 86 108*c3691392SSimon Glass #define TEGRA30_CLK_IRAMD 87 109*c3691392SSimon Glass #define TEGRA30_CLK_CRAM2 88 110*c3691392SSimon Glass /* 89 */ 111*c3691392SSimon Glass #define TEGRA30_CLK_AUDIO_2X 90 /* a/k/a audio_2x_sync_clk */ 112*c3691392SSimon Glass /* 91 */ 113*c3691392SSimon Glass #define TEGRA30_CLK_CSUS 92 114*c3691392SSimon Glass #define TEGRA30_CLK_CDEV2 93 115*c3691392SSimon Glass #define TEGRA30_CLK_CDEV1 94 116*c3691392SSimon Glass /* 95 */ 117*c3691392SSimon Glass 118*c3691392SSimon Glass #define TEGRA30_CLK_CPU_G 96 119*c3691392SSimon Glass #define TEGRA30_CLK_CPU_LP 97 120*c3691392SSimon Glass #define TEGRA30_CLK_GR3D2 98 121*c3691392SSimon Glass #define TEGRA30_CLK_MSELECT 99 122*c3691392SSimon Glass #define TEGRA30_CLK_TSENSOR 100 123*c3691392SSimon Glass #define TEGRA30_CLK_I2S3 101 124*c3691392SSimon Glass #define TEGRA30_CLK_I2S4 102 125*c3691392SSimon Glass #define TEGRA30_CLK_I2C4 103 126*c3691392SSimon Glass #define TEGRA30_CLK_SBC5 104 127*c3691392SSimon Glass #define TEGRA30_CLK_SBC6 105 128*c3691392SSimon Glass #define TEGRA30_CLK_D_AUDIO 106 129*c3691392SSimon Glass #define TEGRA30_CLK_APBIF 107 130*c3691392SSimon Glass #define TEGRA30_CLK_DAM0 108 131*c3691392SSimon Glass #define TEGRA30_CLK_DAM1 109 132*c3691392SSimon Glass #define TEGRA30_CLK_DAM2 110 133*c3691392SSimon Glass #define TEGRA30_CLK_HDA2CODEC_2X 111 134*c3691392SSimon Glass #define TEGRA30_CLK_ATOMICS 112 135*c3691392SSimon Glass #define TEGRA30_CLK_AUDIO0_2X 113 136*c3691392SSimon Glass #define TEGRA30_CLK_AUDIO1_2X 114 137*c3691392SSimon Glass #define TEGRA30_CLK_AUDIO2_2X 115 138*c3691392SSimon Glass #define TEGRA30_CLK_AUDIO3_2X 116 139*c3691392SSimon Glass #define TEGRA30_CLK_AUDIO4_2X 117 140*c3691392SSimon Glass #define TEGRA30_CLK_SPDIF_2X 118 141*c3691392SSimon Glass #define TEGRA30_CLK_ACTMON 119 142*c3691392SSimon Glass #define TEGRA30_CLK_EXTERN1 120 143*c3691392SSimon Glass #define TEGRA30_CLK_EXTERN2 121 144*c3691392SSimon Glass #define TEGRA30_CLK_EXTERN3 122 145*c3691392SSimon Glass #define TEGRA30_CLK_SATA_OOB 123 146*c3691392SSimon Glass #define TEGRA30_CLK_SATA 124 147*c3691392SSimon Glass #define TEGRA30_CLK_HDA 125 148*c3691392SSimon Glass /* 126 */ 149*c3691392SSimon Glass #define TEGRA30_CLK_SE 127 150*c3691392SSimon Glass 151*c3691392SSimon Glass #define TEGRA30_CLK_HDA2HDMI 128 152*c3691392SSimon Glass #define TEGRA30_CLK_SATA_COLD 129 153*c3691392SSimon Glass /* 130 */ 154*c3691392SSimon Glass /* 131 */ 155*c3691392SSimon Glass /* 132 */ 156*c3691392SSimon Glass /* 133 */ 157*c3691392SSimon Glass /* 134 */ 158*c3691392SSimon Glass /* 135 */ 159*c3691392SSimon Glass /* 136 */ 160*c3691392SSimon Glass /* 137 */ 161*c3691392SSimon Glass /* 138 */ 162*c3691392SSimon Glass /* 139 */ 163*c3691392SSimon Glass /* 140 */ 164*c3691392SSimon Glass /* 141 */ 165*c3691392SSimon Glass /* 142 */ 166*c3691392SSimon Glass /* 143 */ 167*c3691392SSimon Glass /* 144 */ 168*c3691392SSimon Glass /* 145 */ 169*c3691392SSimon Glass /* 146 */ 170*c3691392SSimon Glass /* 147 */ 171*c3691392SSimon Glass /* 148 */ 172*c3691392SSimon Glass /* 149 */ 173*c3691392SSimon Glass /* 150 */ 174*c3691392SSimon Glass /* 151 */ 175*c3691392SSimon Glass /* 152 */ 176*c3691392SSimon Glass /* 153 */ 177*c3691392SSimon Glass /* 154 */ 178*c3691392SSimon Glass /* 155 */ 179*c3691392SSimon Glass /* 156 */ 180*c3691392SSimon Glass /* 157 */ 181*c3691392SSimon Glass /* 158 */ 182*c3691392SSimon Glass /* 159 */ 183*c3691392SSimon Glass 184*c3691392SSimon Glass #define TEGRA30_CLK_UARTB 160 185*c3691392SSimon Glass #define TEGRA30_CLK_VFIR 161 186*c3691392SSimon Glass #define TEGRA30_CLK_SPDIF_IN 162 187*c3691392SSimon Glass #define TEGRA30_CLK_SPDIF_OUT 163 188*c3691392SSimon Glass #define TEGRA30_CLK_VI 164 189*c3691392SSimon Glass #define TEGRA30_CLK_VI_SENSOR 165 190*c3691392SSimon Glass #define TEGRA30_CLK_FUSE 166 191*c3691392SSimon Glass #define TEGRA30_CLK_FUSE_BURN 167 192*c3691392SSimon Glass #define TEGRA30_CLK_CVE 168 193*c3691392SSimon Glass #define TEGRA30_CLK_TVO 169 194*c3691392SSimon Glass #define TEGRA30_CLK_CLK_32K 170 195*c3691392SSimon Glass #define TEGRA30_CLK_CLK_M 171 196*c3691392SSimon Glass #define TEGRA30_CLK_CLK_M_DIV2 172 197*c3691392SSimon Glass #define TEGRA30_CLK_CLK_M_DIV4 173 198*c3691392SSimon Glass #define TEGRA30_CLK_PLL_REF 174 199*c3691392SSimon Glass #define TEGRA30_CLK_PLL_C 175 200*c3691392SSimon Glass #define TEGRA30_CLK_PLL_C_OUT1 176 201*c3691392SSimon Glass #define TEGRA30_CLK_PLL_M 177 202*c3691392SSimon Glass #define TEGRA30_CLK_PLL_M_OUT1 178 203*c3691392SSimon Glass #define TEGRA30_CLK_PLL_P 179 204*c3691392SSimon Glass #define TEGRA30_CLK_PLL_P_OUT1 180 205*c3691392SSimon Glass #define TEGRA30_CLK_PLL_P_OUT2 181 206*c3691392SSimon Glass #define TEGRA30_CLK_PLL_P_OUT3 182 207*c3691392SSimon Glass #define TEGRA30_CLK_PLL_P_OUT4 183 208*c3691392SSimon Glass #define TEGRA30_CLK_PLL_A 184 209*c3691392SSimon Glass #define TEGRA30_CLK_PLL_A_OUT0 185 210*c3691392SSimon Glass #define TEGRA30_CLK_PLL_D 186 211*c3691392SSimon Glass #define TEGRA30_CLK_PLL_D_OUT0 187 212*c3691392SSimon Glass #define TEGRA30_CLK_PLL_D2 188 213*c3691392SSimon Glass #define TEGRA30_CLK_PLL_D2_OUT0 189 214*c3691392SSimon Glass #define TEGRA30_CLK_PLL_U 190 215*c3691392SSimon Glass #define TEGRA30_CLK_PLL_X 191 216*c3691392SSimon Glass 217*c3691392SSimon Glass #define TEGRA30_CLK_PLL_X_OUT0 192 218*c3691392SSimon Glass #define TEGRA30_CLK_PLL_E 193 219*c3691392SSimon Glass #define TEGRA30_CLK_SPDIF_IN_SYNC 194 220*c3691392SSimon Glass #define TEGRA30_CLK_I2S0_SYNC 195 221*c3691392SSimon Glass #define TEGRA30_CLK_I2S1_SYNC 196 222*c3691392SSimon Glass #define TEGRA30_CLK_I2S2_SYNC 197 223*c3691392SSimon Glass #define TEGRA30_CLK_I2S3_SYNC 198 224*c3691392SSimon Glass #define TEGRA30_CLK_I2S4_SYNC 199 225*c3691392SSimon Glass #define TEGRA30_CLK_VIMCLK_SYNC 200 226*c3691392SSimon Glass #define TEGRA30_CLK_AUDIO0 201 227*c3691392SSimon Glass #define TEGRA30_CLK_AUDIO1 202 228*c3691392SSimon Glass #define TEGRA30_CLK_AUDIO2 203 229*c3691392SSimon Glass #define TEGRA30_CLK_AUDIO3 204 230*c3691392SSimon Glass #define TEGRA30_CLK_AUDIO4 205 231*c3691392SSimon Glass #define TEGRA30_CLK_SPDIF 206 232*c3691392SSimon Glass #define TEGRA30_CLK_CLK_OUT_1 207 /* (extern1) */ 233*c3691392SSimon Glass #define TEGRA30_CLK_CLK_OUT_2 208 /* (extern2) */ 234*c3691392SSimon Glass #define TEGRA30_CLK_CLK_OUT_3 209 /* (extern3) */ 235*c3691392SSimon Glass #define TEGRA30_CLK_SCLK 210 236*c3691392SSimon Glass #define TEGRA30_CLK_BLINK 211 237*c3691392SSimon Glass #define TEGRA30_CLK_CCLK_G 212 238*c3691392SSimon Glass #define TEGRA30_CLK_CCLK_LP 213 239*c3691392SSimon Glass #define TEGRA30_CLK_TWD 214 240*c3691392SSimon Glass #define TEGRA30_CLK_CML0 215 241*c3691392SSimon Glass #define TEGRA30_CLK_CML1 216 242*c3691392SSimon Glass #define TEGRA30_CLK_HCLK 217 243*c3691392SSimon Glass #define TEGRA30_CLK_PCLK 218 244*c3691392SSimon Glass /* 219 */ 245*c3691392SSimon Glass /* 220 */ 246*c3691392SSimon Glass /* 221 */ 247*c3691392SSimon Glass /* 222 */ 248*c3691392SSimon Glass /* 223 */ 249*c3691392SSimon Glass 250*c3691392SSimon Glass /* 288 */ 251*c3691392SSimon Glass /* 289 */ 252*c3691392SSimon Glass /* 290 */ 253*c3691392SSimon Glass /* 291 */ 254*c3691392SSimon Glass /* 292 */ 255*c3691392SSimon Glass /* 293 */ 256*c3691392SSimon Glass /* 294 */ 257*c3691392SSimon Glass /* 295 */ 258*c3691392SSimon Glass /* 296 */ 259*c3691392SSimon Glass /* 297 */ 260*c3691392SSimon Glass /* 298 */ 261*c3691392SSimon Glass /* 299 */ 262*c3691392SSimon Glass #define TEGRA30_CLK_CLK_OUT_1_MUX 300 263*c3691392SSimon Glass #define TEGRA30_CLK_CLK_OUT_2_MUX 301 264*c3691392SSimon Glass #define TEGRA30_CLK_CLK_OUT_3_MUX 302 265*c3691392SSimon Glass #define TEGRA30_CLK_AUDIO0_MUX 303 266*c3691392SSimon Glass #define TEGRA30_CLK_AUDIO1_MUX 304 267*c3691392SSimon Glass #define TEGRA30_CLK_AUDIO2_MUX 305 268*c3691392SSimon Glass #define TEGRA30_CLK_AUDIO3_MUX 306 269*c3691392SSimon Glass #define TEGRA30_CLK_AUDIO4_MUX 307 270*c3691392SSimon Glass #define TEGRA30_CLK_SPDIF_MUX 308 271*c3691392SSimon Glass #define TEGRA30_CLK_CLK_MAX 309 272*c3691392SSimon Glass 273*c3691392SSimon Glass #endif /* _DT_BINDINGS_CLOCK_TEGRA30_CAR_H */ 274