1*a0e79083SPurna Chandra Mandal /* 2*a0e79083SPurna Chandra Mandal * (c) 2015 Purna Chandra Mandal <purna.mandal@microchip.com> 3*a0e79083SPurna Chandra Mandal * 4*a0e79083SPurna Chandra Mandal * SPDX-License-Identifier: GPL-2.0+ 5*a0e79083SPurna Chandra Mandal * 6*a0e79083SPurna Chandra Mandal */ 7*a0e79083SPurna Chandra Mandal 8*a0e79083SPurna Chandra Mandal #ifndef __CLK_MICROCHIP_PIC32 9*a0e79083SPurna Chandra Mandal #define __CLK_MICROCHIP_PIC32 10*a0e79083SPurna Chandra Mandal 11*a0e79083SPurna Chandra Mandal /* clock output indices */ 12*a0e79083SPurna Chandra Mandal #define BASECLK 0 13*a0e79083SPurna Chandra Mandal #define PLLCLK 1 14*a0e79083SPurna Chandra Mandal #define MPLL 2 15*a0e79083SPurna Chandra Mandal #define SYSCLK 3 16*a0e79083SPurna Chandra Mandal #define PB1CLK 4 17*a0e79083SPurna Chandra Mandal #define PB2CLK 5 18*a0e79083SPurna Chandra Mandal #define PB3CLK 6 19*a0e79083SPurna Chandra Mandal #define PB4CLK 7 20*a0e79083SPurna Chandra Mandal #define PB5CLK 8 21*a0e79083SPurna Chandra Mandal #define PB6CLK 9 22*a0e79083SPurna Chandra Mandal #define PB7CLK 10 23*a0e79083SPurna Chandra Mandal #define REF1CLK 11 24*a0e79083SPurna Chandra Mandal #define REF2CLK 12 25*a0e79083SPurna Chandra Mandal #define REF3CLK 13 26*a0e79083SPurna Chandra Mandal #define REF4CLK 14 27*a0e79083SPurna Chandra Mandal #define REF5CLK 15 28*a0e79083SPurna Chandra Mandal 29*a0e79083SPurna Chandra Mandal #endif /* __CLK_MICROCHIP_PIC32 */ 30