1/* 2 * Copyright (C) 2013 Altera Corporation 3 * 4 * This file is generated by sopc2dts. 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9/dts-v1/; 10 11/ { 12 model = "altr,qsys_ghrd_3c120"; 13 compatible = "altr,qsys_ghrd_3c120"; 14 #address-cells = <1>; 15 #size-cells = <1>; 16 17 cpus { 18 #address-cells = <1>; 19 #size-cells = <0>; 20 21 cpu: cpu@0x0 { 22 device_type = "cpu"; 23 compatible = "altr,nios2-1.0"; 24 reg = <0x00000000>; 25 interrupt-controller; 26 #interrupt-cells = <1>; 27 clock-frequency = <125000000>; 28 dcache-line-size = <32>; 29 icache-line-size = <32>; 30 dcache-size = <32768>; 31 icache-size = <32768>; 32 altr,implementation = "fast"; 33 altr,pid-num-bits = <8>; 34 altr,tlb-num-ways = <16>; 35 altr,tlb-num-entries = <128>; 36 altr,tlb-ptr-sz = <7>; 37 altr,has-div = <1>; 38 altr,has-mul = <1>; 39 altr,reset-addr = <0xc2800000>; 40 altr,fast-tlb-miss-addr = <0xc7fff400>; 41 altr,exception-addr = <0xd0000020>; 42 altr,has-initda = <1>; 43 altr,has-mmu = <1>; 44 }; 45 }; 46 47 memory@0 { 48 device_type = "memory"; 49 reg = <0x10000000 0x08000000>, 50 <0x07fff400 0x00000400>; 51 }; 52 53 sopc@0 { 54 device_type = "soc"; 55 ranges; 56 #address-cells = <1>; 57 #size-cells = <1>; 58 compatible = "altr,avalon", "simple-bus"; 59 bus-frequency = <125000000>; 60 61 pb_cpu_to_io: bridge@0x8000000 { 62 compatible = "simple-bus"; 63 reg = <0x08000000 0x00800000>; 64 #address-cells = <1>; 65 #size-cells = <1>; 66 ranges = <0x00002000 0x08002000 0x00002000>, 67 <0x00004000 0x08004000 0x00000400>, 68 <0x00004400 0x08004400 0x00000040>, 69 <0x00004800 0x08004800 0x00000040>, 70 <0x00004c80 0x08004c80 0x00000020>, 71 <0x00004d50 0x08004d50 0x00000008>, 72 <0x00008000 0x08008000 0x00000020>, 73 <0x00400000 0x08400000 0x00000020>; 74 75 timer_1ms: timer@0x400000 { 76 compatible = "altr,timer-1.0"; 77 reg = <0x00400000 0x00000020>; 78 interrupt-parent = <&cpu>; 79 interrupts = <11>; 80 clock-frequency = <125000000>; 81 }; 82 83 timer_0: timer@0x8000 { 84 compatible = "altr,timer-1.0"; 85 reg = < 0x00008000 0x00000020 >; 86 interrupt-parent = < &cpu >; 87 interrupts = < 5 >; 88 clock-frequency = < 125000000 >; 89 }; 90 91 jtag_uart: serial@0x4d50 { 92 compatible = "altr,juart-1.0"; 93 reg = <0x00004d50 0x00000008>; 94 interrupt-parent = <&cpu>; 95 interrupts = <1>; 96 }; 97 98 tse_mac: ethernet@0x4000 { 99 compatible = "altr,tse-1.0"; 100 reg = <0x00004000 0x00000400>, 101 <0x00004400 0x00000040>, 102 <0x00004800 0x00000040>, 103 <0x00002000 0x00002000>; 104 reg-names = "control_port", "rx_csr", "tx_csr", "s1"; 105 interrupt-parent = <&cpu>; 106 interrupts = <2 3>; 107 interrupt-names = "rx_irq", "tx_irq"; 108 rx-fifo-depth = <8192>; 109 tx-fifo-depth = <8192>; 110 max-frame-size = <1518>; 111 local-mac-address = [ 00 00 00 00 00 00 ]; 112 phy-mode = "rgmii-id"; 113 phy-handle = <&phy0>; 114 tse_mac_mdio: mdio { 115 compatible = "altr,tse-mdio"; 116 #address-cells = <1>; 117 #size-cells = <0>; 118 phy0: ethernet-phy@18 { 119 reg = <18>; 120 device_type = "ethernet-phy"; 121 }; 122 }; 123 }; 124 125 uart: serial@0x4c80 { 126 compatible = "altr,uart-1.0"; 127 reg = <0x00004c80 0x00000020>; 128 interrupt-parent = <&cpu>; 129 interrupts = <10>; 130 current-speed = <115200>; 131 clock-frequency = <62500000>; 132 }; 133 }; 134 135 cfi_flash_64m: flash@0x0 { 136 compatible = "cfi-flash"; 137 reg = <0x00000000 0x04000000>; 138 bank-width = <2>; 139 device-width = <1>; 140 #address-cells = <1>; 141 #size-cells = <1>; 142 143 partition@800000 { 144 reg = <0x00800000 0x01e00000>; 145 label = "JFFS2 Filesystem"; 146 }; 147 }; 148 }; 149 150 chosen { 151 bootargs = "debug console=ttyJ0,115200"; 152 }; 153}; 154