1// SPDX-License-Identifier: GPL-2.0+
2/*
3 *  Copyright (C) 2013 Altera Corporation
4 *
5 * This file is generated by sopc2dts.
6 */
7
8/dts-v1/;
9
10/ {
11	model = "altr,qsys_ghrd_3c120";
12	compatible = "altr,qsys_ghrd_3c120";
13	#address-cells = <1>;
14	#size-cells = <1>;
15
16	cpus {
17		#address-cells = <1>;
18		#size-cells = <0>;
19
20		cpu: cpu@0x0 {
21			device_type = "cpu";
22			compatible = "altr,nios2-1.0";
23			reg = <0x00000000>;
24			interrupt-controller;
25			#interrupt-cells = <1>;
26			clock-frequency = <125000000>;
27			dcache-line-size = <32>;
28			icache-line-size = <32>;
29			dcache-size = <32768>;
30			icache-size = <32768>;
31			altr,implementation = "fast";
32			altr,pid-num-bits = <8>;
33			altr,tlb-num-ways = <16>;
34			altr,tlb-num-entries = <128>;
35			altr,tlb-ptr-sz = <7>;
36			altr,has-div = <1>;
37			altr,has-mul = <1>;
38			altr,reset-addr = <0xc2800000>;
39			altr,fast-tlb-miss-addr = <0xc7fff400>;
40			altr,exception-addr = <0xd0000020>;
41			altr,has-initda = <1>;
42			altr,has-mmu = <1>;
43		};
44	};
45
46	memory@0 {
47		device_type = "memory";
48		reg = <0x10000000 0x08000000>,
49			<0x07fff400 0x00000400>;
50	};
51
52	sopc@0 {
53		device_type = "soc";
54		ranges;
55		#address-cells = <1>;
56		#size-cells = <1>;
57		compatible = "altr,avalon", "simple-bus";
58		bus-frequency = <125000000>;
59
60		pb_cpu_to_io: bridge@0x8000000 {
61			compatible = "simple-bus";
62			reg = <0x08000000 0x00800000>;
63			#address-cells = <1>;
64			#size-cells = <1>;
65			ranges = <0x00002000 0x08002000 0x00002000>,
66				<0x00004000 0x08004000 0x00000400>,
67				<0x00004400 0x08004400 0x00000040>,
68				<0x00004800 0x08004800 0x00000040>,
69				<0x00004c80 0x08004c80 0x00000020>,
70				<0x00004cc0 0x08004cc0 0x00000010>,
71				<0x00004ce0 0x08004ce0 0x00000010>,
72				<0x00004d00 0x08004d00 0x00000010>,
73				<0x00004d40 0x08004d40 0x00000008>,
74				<0x00004d50 0x08004d50 0x00000008>,
75				<0x00008000 0x08008000 0x00000020>,
76				<0x00400000 0x08400000 0x00000020>;
77
78			timer_1ms: timer@0x400000 {
79				compatible = "altr,timer-1.0";
80				reg = <0x00400000 0x00000020>;
81				interrupt-parent = <&cpu>;
82				interrupts = <11>;
83				clock-frequency = <125000000>;
84			};
85
86			timer_0: timer@0x8000 {
87				compatible = "altr,timer-1.0";
88				reg = < 0x00008000 0x00000020 >;
89				interrupt-parent = < &cpu >;
90				interrupts = < 5 >;
91				clock-frequency = < 125000000 >;
92			};
93
94			sysid: sysid@0x4d40 {
95				compatible = "altr,sysid-1.0";
96				reg = <0x00004d40 0x00000008>;
97			};
98
99			jtag_uart: serial@0x4d50 {
100				compatible = "altr,juart-1.0";
101				reg = <0x00004d50 0x00000008>;
102				interrupt-parent = <&cpu>;
103				interrupts = <1>;
104			};
105
106			tse_mac: ethernet@0x4000 {
107				compatible = "altr,tse-1.0";
108				reg = <0x00004000 0x00000400>,
109					<0x00004400 0x00000040>,
110					<0x00004800 0x00000040>,
111					<0x00002000 0x00002000>;
112				reg-names = "control_port", "rx_csr", "tx_csr", "s1";
113				interrupt-parent = <&cpu>;
114				interrupts = <2 3>;
115				interrupt-names = "rx_irq", "tx_irq";
116				rx-fifo-depth = <8192>;
117				tx-fifo-depth = <8192>;
118				max-frame-size = <1518>;
119				local-mac-address = [ 00 00 00 00 00 00 ];
120				phy-mode = "rgmii-id";
121				phy-handle = <&phy0>;
122				tse_mac_mdio: mdio {
123					compatible = "altr,tse-mdio";
124					#address-cells = <1>;
125					#size-cells = <0>;
126					phy0: ethernet-phy@18 {
127						reg = <18>;
128						device_type = "ethernet-phy";
129					};
130				};
131			};
132
133			uart: serial@0x4c80 {
134				compatible = "altr,uart-1.0";
135				reg = <0x00004c80 0x00000020>;
136				interrupt-parent = <&cpu>;
137				interrupts = <10>;
138				current-speed = <115200>;
139				clock-frequency = <62500000>;
140			};
141
142			user_led_pio_8out: gpio@0x4cc0 {
143				compatible = "altr,pio-1.0";
144				reg = <0x00004cc0 0x00000010>;
145				resetvalue = <255>;
146				altr,gpio-bank-width = <8>;
147				#gpio-cells = <2>;
148				gpio-controller;
149				gpio-bank-name = "led";
150			};
151
152			user_dipsw_pio_8in: gpio@0x4ce0 {
153				compatible = "altr,pio-1.0";
154				reg = <0x00004ce0 0x00000010>;
155				interrupt-parent = <&cpu>;
156				interrupts = <8>;
157				edge_type = <2>;
158				level_trigger = <0>;
159				resetvalue = <0>;
160				altr,gpio-bank-width = <8>;
161				#gpio-cells = <2>;
162				gpio-controller;
163				gpio-bank-name = "dipsw";
164			};
165
166			user_pb_pio_4in: gpio@0x4d00 {
167				compatible = "altr,pio-1.0";
168				reg = <0x00004d00 0x00000010>;
169				interrupt-parent = <&cpu>;
170				interrupts = <9>;
171				edge_type = <2>;
172				level_trigger = <0>;
173				resetvalue = <0>;
174				altr,gpio-bank-width = <4>;
175				#gpio-cells = <2>;
176				gpio-controller;
177				gpio-bank-name = "pb";
178			};
179		};
180
181		cfi_flash_64m: flash@0x0 {
182			compatible = "cfi-flash";
183			reg = <0x00000000 0x04000000>;
184			bank-width = <2>;
185			device-width = <1>;
186			#address-cells = <1>;
187			#size-cells = <1>;
188
189			partition@800000 {
190				reg = <0x00800000 0x01e00000>;
191				label = "JFFS2 Filesystem";
192			};
193		};
194	};
195
196	chosen {
197		bootargs = "debug console=ttyJ0,115200";
198		stdout-path = &jtag_uart;
199	};
200};
201