1/*
2 *  Copyright (C) 2015 Altera Corporation
3 *
4 * This file is generated by sopc2dts.
5 *
6 * SPDX-License-Identifier:	GPL-2.0+
7 */
8
9/dts-v1/;
10
11/ {
12	model = "Altera NiosII Max10";
13	compatible = "altr,niosii-max10";
14	#address-cells = <1>;
15	#size-cells = <1>;
16
17	cpus {
18		#address-cells = <1>;
19		#size-cells = <0>;
20
21		cpu: cpu@0 {
22			device_type = "cpu";
23			compatible = "altr,nios2-1.1";
24			reg = <0x00000000>;
25			interrupt-controller;
26			#interrupt-cells = <1>;
27			altr,exception-addr = <0xc8000120>;
28			altr,fast-tlb-miss-addr = <0xc0000100>;
29			altr,has-div = <1>;
30			altr,has-initda = <1>;
31			altr,has-mmu = <1>;
32			altr,has-mul = <1>;
33			altr,implementation = "fast";
34			altr,pid-num-bits = <8>;
35			altr,reset-addr = <0xd4000000>;
36			altr,tlb-num-entries = <256>;
37			altr,tlb-num-ways = <16>;
38			altr,tlb-ptr-sz = <8>;
39			clock-frequency = <75000000>;
40			dcache-line-size = <32>;
41			dcache-size = <32768>;
42			icache-line-size = <32>;
43			icache-size = <32768>;
44		};
45	};
46
47	memory {
48		device_type = "memory";
49		reg = <0x08000000 0x08000000>,
50			<0x00000000 0x00000400>;
51	};
52
53	sopc0: sopc@0 {
54		device_type = "soc";
55		ranges;
56		#address-cells = <1>;
57		#size-cells = <1>;
58		compatible = "altr,avalon", "simple-bus";
59		bus-frequency = <75000000>;
60
61		jtag_uart: serial@18001530 {
62			compatible = "altr,juart-1.0";
63			reg = <0x18001530 0x00000008>;
64			interrupt-parent = <&cpu>;
65			interrupts = <7>;
66		};
67
68		a_16550_uart_0: serial@18001600 {
69			compatible = "altr,16550-FIFO32", "ns16550a";
70			reg = <0x18001600 0x00000200>;
71			interrupt-parent = <&cpu>;
72			interrupts = <1>;
73			auto-flow-control = <1>;
74			clock-frequency = <50000000>;
75			fifo-size = <32>;
76			reg-io-width = <4>;
77			reg-shift = <2>;
78		};
79
80		ext_flash: quadspi@0x180014a0 {
81			compatible = "altr,quadspi-1.0";
82			reg = <0x180014a0 0x00000020>,
83				<0x14000000 0x04000000>;
84			reg-names = "avl_csr", "avl_mem";
85			interrupt-parent = <&cpu>;
86			interrupts = <4>;
87			#address-cells = <1>;
88			#size-cells = <0>;
89			flash0: nor0@0 {
90				compatible = "micron,n25q512a";
91				#address-cells = <1>;
92				#size-cells = <1>;
93			};
94		};
95
96		sysid: sysid@18001528 {
97			compatible = "altr,sysid-1.0";
98			reg = <0x18001528 0x00000008>;
99		};
100
101		rgmii_0_eth_tse_0: ethernet@400 {
102			compatible = "altr,tse-msgdma-1.0", "altr,tse-1.0";
103			reg = <0x00000400 0x00000400>,
104				<0x00000820 0x00000020>,
105				<0x00000800 0x00000020>,
106				<0x000008c0 0x00000008>,
107				<0x00000840 0x00000020>,
108				<0x00000860 0x00000020>;
109			reg-names = "control_port", "rx_csr", "rx_desc", "rx_resp",
110				  "tx_csr", "tx_desc";
111			interrupt-parent = <&cpu>;
112			interrupts = <2 3>;
113			interrupt-names = "rx_irq", "tx_irq";
114			rx-fifo-depth = <8192>;
115			tx-fifo-depth = <8192>;
116			address-bits = <48>;
117			max-frame-size = <1518>;
118			local-mac-address = [00 00 00 00 00 00];
119			altr,has-supplementary-unicast;
120			altr,enable-sup-addr = <1>;
121			altr,has-hash-multicast-filter;
122			altr,enable-hash = <1>;
123			phy-mode = "rgmii-id";
124			phy-handle = <&phy0>;
125			rgmii_0_eth_tse_0_mdio: mdio {
126				compatible = "altr,tse-mdio";
127				#address-cells = <1>;
128				#size-cells = <0>;
129				phy0: ethernet-phy@0 {
130					reg = <0>;
131					device_type = "ethernet-phy";
132				};
133			};
134		};
135
136		enet_pll: clock@0 {
137			compatible = "altr,pll-1.0";
138			#clock-cells = <1>;
139
140			enet_pll_c0: enet_pll_c0 {
141				compatible = "fixed-clock";
142				#clock-cells = <0>;
143				clock-frequency = <125000000>;
144				clock-output-names = "enet_pll-c0";
145			};
146
147			enet_pll_c1: enet_pll_c1 {
148				compatible = "fixed-clock";
149				#clock-cells = <0>;
150				clock-frequency = <25000000>;
151				clock-output-names = "enet_pll-c1";
152			};
153
154			enet_pll_c2: enet_pll_c2 {
155				compatible = "fixed-clock";
156				#clock-cells = <0>;
157				clock-frequency = <2500000>;
158				clock-output-names = "enet_pll-c2";
159			};
160		};
161
162		sys_pll: clock@1 {
163			compatible = "altr,pll-1.0";
164			#clock-cells = <1>;
165
166			sys_pll_c0: sys_pll_c0 {
167				compatible = "fixed-clock";
168				#clock-cells = <0>;
169				clock-frequency = <100000000>;
170				clock-output-names = "sys_pll-c0";
171			};
172
173			sys_pll_c1: sys_pll_c1 {
174				compatible = "fixed-clock";
175				#clock-cells = <0>;
176				clock-frequency = <50000000>;
177				clock-output-names = "sys_pll-c1";
178			};
179
180			sys_pll_c2: sys_pll_c2 {
181				compatible = "fixed-clock";
182				#clock-cells = <0>;
183				clock-frequency = <75000000>;
184				clock-output-names = "sys_pll-c2";
185			};
186		};
187
188		sys_clk_timer: timer@18001440 {
189			compatible = "altr,timer-1.0";
190			reg = <0x18001440 0x00000020>;
191			interrupt-parent = <&cpu>;
192			interrupts = <0>;
193			clock-frequency = <75000000>;
194		};
195
196		led_pio: gpio@180014d0 {
197			compatible = "altr,pio-1.0";
198			reg = <0x180014d0 0x00000010>;
199			altr,gpio-bank-width = <4>;
200			resetvalue = <15>;
201			#gpio-cells = <2>;
202			gpio-controller;
203			gpio-bank-name = "led";
204		};
205
206		uart_0: serial@0x18001420 {
207			compatible = "altr,uart-1.0";
208			reg = <0x18001420 0x00000020>;
209			interrupt-parent = <&cpu>;
210			interrupts = <1>;
211			clock-frequency = <75000000>;
212			current-speed = <115200>;
213		};
214
215		button_pio: gpio@180014c0 {
216			compatible = "altr,pio-1.0";
217			reg = <0x180014c0 0x00000010>;
218			interrupt-parent = <&cpu>;
219			interrupts = <6>;
220			altr,gpio-bank-width = <3>;
221			altr,interrupt-type = <2>;
222			edge_type = <1>;
223			level_trigger = <0>;
224			resetvalue = <0>;
225			#gpio-cells = <2>;
226			gpio-controller;
227			gpio-bank-name = "button";
228		};
229
230		sys_clk_timer_1: timer@880 {
231			compatible = "altr,timer-1.0";
232			reg = <0x00000880 0x00000020>;
233			interrupt-parent = <&cpu>;
234			interrupts = <5>;
235			clock-frequency = <75000000>;
236		};
237
238		fpga_leds: leds {
239			compatible = "gpio-leds";
240
241			led_fpga0: fpga0 {
242				label = "fpga_led0";
243				gpios = <&led_pio 0 1>;
244			};
245
246			led_fpga1: fpga1 {
247				label = "fpga_led1";
248				gpios = <&led_pio 1 1>;
249			};
250
251			led_fpga2: fpga2 {
252				label = "fpga_led2";
253				gpios = <&led_pio 2 1>;
254			};
255
256			led_fpga3: fpga3 {
257				label = "fpga_led3";
258				gpios = <&led_pio 3 1>;
259			};
260		};
261	};
262
263	chosen {
264		bootargs = "debug console=ttyS0,115200";
265		stdout-path = &a_16550_uart_0;
266	};
267};
268