1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * (C) Copyright 2004, Psyent Corporation <www.psyent.com> 4 * Scott McNutt <smcnutt@psyent.com> 5 */ 6 7 #include <common.h> 8 #include <cpu.h> 9 #include <dm.h> 10 #include <errno.h> 11 #include <asm/cache.h> 12 13 DECLARE_GLOBAL_DATA_PTR; 14 15 #ifdef CONFIG_DISPLAY_CPUINFO 16 int print_cpuinfo(void) 17 { 18 printf("CPU: Nios-II\n"); 19 return 0; 20 } 21 #endif /* CONFIG_DISPLAY_CPUINFO */ 22 23 #ifdef CONFIG_ALTERA_SYSID 24 int checkboard(void) 25 { 26 display_sysid(); 27 return 0; 28 } 29 #endif 30 31 int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) 32 { 33 disable_interrupts(); 34 /* indirect call to go beyond 256MB limitation of toolchain */ 35 nios2_callr(gd->arch.reset_addr); 36 return 0; 37 } 38 39 /* 40 * COPY EXCEPTION TRAMPOLINE -- copy the tramp to the 41 * exception address. Define CONFIG_ROM_STUBS to prevent 42 * the copy (e.g. exception in flash or in other 43 * softare/firmware component). 44 */ 45 #ifndef CONFIG_ROM_STUBS 46 static void copy_exception_trampoline(void) 47 { 48 extern int _except_start, _except_end; 49 void *except_target = (void *)gd->arch.exception_addr; 50 51 if (&_except_start != except_target) { 52 memcpy(except_target, &_except_start, 53 &_except_end - &_except_start); 54 flush_cache(gd->arch.exception_addr, 55 &_except_end - &_except_start); 56 } 57 } 58 #endif 59 60 int arch_cpu_init_dm(void) 61 { 62 struct udevice *dev; 63 int ret; 64 65 ret = uclass_first_device_err(UCLASS_CPU, &dev); 66 if (ret) 67 return ret; 68 69 gd->ram_size = CONFIG_SYS_SDRAM_SIZE; 70 #ifndef CONFIG_ROM_STUBS 71 copy_exception_trampoline(); 72 #endif 73 74 return 0; 75 } 76 77 static int altera_nios2_get_desc(struct udevice *dev, char *buf, int size) 78 { 79 const char *cpu_name = "Nios-II"; 80 81 if (size < strlen(cpu_name)) 82 return -ENOSPC; 83 strcpy(buf, cpu_name); 84 85 return 0; 86 } 87 88 static int altera_nios2_get_info(struct udevice *dev, struct cpu_info *info) 89 { 90 info->cpu_freq = gd->cpu_clk; 91 info->features = (1 << CPU_FEAT_L1_CACHE) | 92 (gd->arch.has_mmu ? (1 << CPU_FEAT_MMU) : 0); 93 94 return 0; 95 } 96 97 static int altera_nios2_get_count(struct udevice *dev) 98 { 99 return 1; 100 } 101 102 static int altera_nios2_probe(struct udevice *dev) 103 { 104 const void *blob = gd->fdt_blob; 105 int node = dev_of_offset(dev); 106 107 gd->cpu_clk = fdtdec_get_int(blob, node, 108 "clock-frequency", 0); 109 gd->arch.dcache_line_size = fdtdec_get_int(blob, node, 110 "dcache-line-size", 0); 111 gd->arch.icache_line_size = fdtdec_get_int(blob, node, 112 "icache-line-size", 0); 113 gd->arch.dcache_size = fdtdec_get_int(blob, node, 114 "dcache-size", 0); 115 gd->arch.icache_size = fdtdec_get_int(blob, node, 116 "icache-size", 0); 117 gd->arch.reset_addr = fdtdec_get_int(blob, node, 118 "altr,reset-addr", 0); 119 gd->arch.exception_addr = fdtdec_get_int(blob, node, 120 "altr,exception-addr", 0); 121 gd->arch.has_initda = fdtdec_get_int(blob, node, 122 "altr,has-initda", 0); 123 gd->arch.has_mmu = fdtdec_get_int(blob, node, 124 "altr,has-mmu", 0); 125 gd->arch.io_region_base = gd->arch.has_mmu ? 0xe0000000 : 0x80000000; 126 gd->arch.mem_region_base = gd->arch.has_mmu ? 0xc0000000 : 0x00000000; 127 gd->arch.physaddr_mask = gd->arch.has_mmu ? 0x1fffffff : 0x7fffffff; 128 129 return 0; 130 } 131 132 static const struct cpu_ops altera_nios2_ops = { 133 .get_desc = altera_nios2_get_desc, 134 .get_info = altera_nios2_get_info, 135 .get_count = altera_nios2_get_count, 136 }; 137 138 static const struct udevice_id altera_nios2_ids[] = { 139 { .compatible = "altr,nios2-1.0" }, 140 { .compatible = "altr,nios2-1.1" }, 141 { } 142 }; 143 144 U_BOOT_DRIVER(altera_nios2) = { 145 .name = "altera_nios2", 146 .id = UCLASS_CPU, 147 .of_match = altera_nios2_ids, 148 .probe = altera_nios2_probe, 149 .ops = &altera_nios2_ops, 150 .flags = DM_FLAG_PRE_RELOC, 151 }; 152 153 /* This is a dummy function on nios2 */ 154 int dram_init(void) 155 { 156 return 0; 157 } 158