1 /* 2 * (C) Copyright 2004, Psyent Corporation <www.psyent.com> 3 * Scott McNutt <smcnutt@psyent.com> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #include <common.h> 9 #include <cpu.h> 10 #include <dm.h> 11 #include <errno.h> 12 #include <asm/cache.h> 13 14 DECLARE_GLOBAL_DATA_PTR; 15 16 #if defined (CONFIG_SYS_NIOS_SYSID_BASE) 17 extern void display_sysid (void); 18 #endif /* CONFIG_SYS_NIOS_SYSID_BASE */ 19 20 #ifdef CONFIG_DISPLAY_CPUINFO 21 int print_cpuinfo(void) 22 { 23 printf ("CPU : Nios-II\n"); 24 #if !defined(CONFIG_SYS_NIOS_SYSID_BASE) 25 printf ("SYSID : <unknown>\n"); 26 #else 27 display_sysid (); 28 #endif 29 return (0); 30 } 31 #endif /* CONFIG_DISPLAY_CPUINFO */ 32 33 int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) 34 { 35 disable_interrupts(); 36 /* indirect call to go beyond 256MB limitation of toolchain */ 37 nios2_callr(CONFIG_SYS_RESET_ADDR); 38 return 0; 39 } 40 41 int dcache_status(void) 42 { 43 return 1; 44 } 45 46 void dcache_enable(void) 47 { 48 flush_dcache(CONFIG_SYS_DCACHE_SIZE, CONFIG_SYS_DCACHELINE_SIZE); 49 } 50 51 void dcache_disable(void) 52 { 53 flush_dcache(CONFIG_SYS_DCACHE_SIZE, CONFIG_SYS_DCACHELINE_SIZE); 54 } 55 56 int arch_cpu_init_dm(void) 57 { 58 struct udevice *dev; 59 int ret; 60 61 ret = uclass_first_device(UCLASS_CPU, &dev); 62 if (ret) 63 return ret; 64 if (!dev) 65 return -ENODEV; 66 67 gd->ram_size = CONFIG_SYS_SDRAM_SIZE; 68 69 return 0; 70 } 71 72 static int altera_nios2_get_desc(struct udevice *dev, char *buf, int size) 73 { 74 const char *cpu_name = "Nios-II"; 75 76 if (size < strlen(cpu_name)) 77 return -ENOSPC; 78 strcpy(buf, cpu_name); 79 80 return 0; 81 } 82 83 static int altera_nios2_get_info(struct udevice *dev, struct cpu_info *info) 84 { 85 info->cpu_freq = gd->cpu_clk; 86 info->features = (1 << CPU_FEAT_L1_CACHE) | 87 (gd->arch.has_mmu ? (1 << CPU_FEAT_MMU) : 0); 88 89 return 0; 90 } 91 92 static int altera_nios2_get_count(struct udevice *dev) 93 { 94 return 1; 95 } 96 97 static int altera_nios2_probe(struct udevice *dev) 98 { 99 const void *blob = gd->fdt_blob; 100 int node = dev->of_offset; 101 102 gd->cpu_clk = fdtdec_get_int(blob, node, 103 "clock-frequency", 0); 104 gd->arch.dcache_line_size = fdtdec_get_int(blob, node, 105 "dcache-line-size", 0); 106 gd->arch.icache_line_size = fdtdec_get_int(blob, node, 107 "icache-line-size", 0); 108 gd->arch.dcache_size = fdtdec_get_int(blob, node, 109 "dcache-size", 0); 110 gd->arch.icache_size = fdtdec_get_int(blob, node, 111 "icache-size", 0); 112 gd->arch.reset_addr = fdtdec_get_int(blob, node, 113 "altr,reset-addr", 0); 114 gd->arch.exception_addr = fdtdec_get_int(blob, node, 115 "altr,exception-addr", 0); 116 gd->arch.has_initda = fdtdec_get_int(blob, node, 117 "altr,has-initda", 0); 118 gd->arch.has_mmu = fdtdec_get_int(blob, node, 119 "altr,has-mmu", 0); 120 gd->arch.io_region_base = gd->arch.has_mmu ? 0xe0000000 : 0x8000000; 121 122 return 0; 123 } 124 125 static const struct cpu_ops altera_nios2_ops = { 126 .get_desc = altera_nios2_get_desc, 127 .get_info = altera_nios2_get_info, 128 .get_count = altera_nios2_get_count, 129 }; 130 131 static const struct udevice_id altera_nios2_ids[] = { 132 { .compatible = "altr,nios2-1.0" }, 133 { .compatible = "altr,nios2-1.1" }, 134 { } 135 }; 136 137 U_BOOT_DRIVER(altera_nios2) = { 138 .name = "altera_nios2", 139 .id = UCLASS_CPU, 140 .of_match = altera_nios2_ids, 141 .probe = altera_nios2_probe, 142 .ops = &altera_nios2_ops, 143 .flags = DM_FLAG_PRE_RELOC, 144 }; 145