1 /* 2 * (C) Copyright 2004, Psyent Corporation <www.psyent.com> 3 * Scott McNutt <smcnutt@psyent.com> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #include <common.h> 9 #include <cpu.h> 10 #include <dm.h> 11 #include <errno.h> 12 #include <asm/cache.h> 13 14 DECLARE_GLOBAL_DATA_PTR; 15 16 #ifdef CONFIG_DISPLAY_CPUINFO 17 int print_cpuinfo(void) 18 { 19 printf("CPU: Nios-II\n"); 20 return 0; 21 } 22 #endif /* CONFIG_DISPLAY_CPUINFO */ 23 24 #ifdef CONFIG_ALTERA_SYSID 25 int checkboard(void) 26 { 27 display_sysid(); 28 return 0; 29 } 30 #endif 31 32 int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) 33 { 34 disable_interrupts(); 35 /* indirect call to go beyond 256MB limitation of toolchain */ 36 nios2_callr(gd->arch.reset_addr); 37 return 0; 38 } 39 40 /* 41 * COPY EXCEPTION TRAMPOLINE -- copy the tramp to the 42 * exception address. Define CONFIG_ROM_STUBS to prevent 43 * the copy (e.g. exception in flash or in other 44 * softare/firmware component). 45 */ 46 #ifndef CONFIG_ROM_STUBS 47 static void copy_exception_trampoline(void) 48 { 49 extern int _except_start, _except_end; 50 void *except_target = (void *)gd->arch.exception_addr; 51 52 if (&_except_start != except_target) { 53 memcpy(except_target, &_except_start, 54 &_except_end - &_except_start); 55 flush_cache(gd->arch.exception_addr, 56 &_except_end - &_except_start); 57 } 58 } 59 #endif 60 61 int arch_cpu_init_dm(void) 62 { 63 struct udevice *dev; 64 int ret; 65 66 ret = uclass_first_device_err(UCLASS_CPU, &dev); 67 if (ret) 68 return ret; 69 70 gd->ram_size = CONFIG_SYS_SDRAM_SIZE; 71 #ifndef CONFIG_ROM_STUBS 72 copy_exception_trampoline(); 73 #endif 74 75 return 0; 76 } 77 78 static int altera_nios2_get_desc(struct udevice *dev, char *buf, int size) 79 { 80 const char *cpu_name = "Nios-II"; 81 82 if (size < strlen(cpu_name)) 83 return -ENOSPC; 84 strcpy(buf, cpu_name); 85 86 return 0; 87 } 88 89 static int altera_nios2_get_info(struct udevice *dev, struct cpu_info *info) 90 { 91 info->cpu_freq = gd->cpu_clk; 92 info->features = (1 << CPU_FEAT_L1_CACHE) | 93 (gd->arch.has_mmu ? (1 << CPU_FEAT_MMU) : 0); 94 95 return 0; 96 } 97 98 static int altera_nios2_get_count(struct udevice *dev) 99 { 100 return 1; 101 } 102 103 static int altera_nios2_probe(struct udevice *dev) 104 { 105 const void *blob = gd->fdt_blob; 106 int node = dev_of_offset(dev); 107 108 gd->cpu_clk = fdtdec_get_int(blob, node, 109 "clock-frequency", 0); 110 gd->arch.dcache_line_size = fdtdec_get_int(blob, node, 111 "dcache-line-size", 0); 112 gd->arch.icache_line_size = fdtdec_get_int(blob, node, 113 "icache-line-size", 0); 114 gd->arch.dcache_size = fdtdec_get_int(blob, node, 115 "dcache-size", 0); 116 gd->arch.icache_size = fdtdec_get_int(blob, node, 117 "icache-size", 0); 118 gd->arch.reset_addr = fdtdec_get_int(blob, node, 119 "altr,reset-addr", 0); 120 gd->arch.exception_addr = fdtdec_get_int(blob, node, 121 "altr,exception-addr", 0); 122 gd->arch.has_initda = fdtdec_get_int(blob, node, 123 "altr,has-initda", 0); 124 gd->arch.has_mmu = fdtdec_get_int(blob, node, 125 "altr,has-mmu", 0); 126 gd->arch.io_region_base = gd->arch.has_mmu ? 0xe0000000 : 0x80000000; 127 gd->arch.mem_region_base = gd->arch.has_mmu ? 0xc0000000 : 0x00000000; 128 gd->arch.physaddr_mask = gd->arch.has_mmu ? 0x1fffffff : 0x7fffffff; 129 130 return 0; 131 } 132 133 static const struct cpu_ops altera_nios2_ops = { 134 .get_desc = altera_nios2_get_desc, 135 .get_info = altera_nios2_get_info, 136 .get_count = altera_nios2_get_count, 137 }; 138 139 static const struct udevice_id altera_nios2_ids[] = { 140 { .compatible = "altr,nios2-1.0" }, 141 { .compatible = "altr,nios2-1.1" }, 142 { } 143 }; 144 145 U_BOOT_DRIVER(altera_nios2) = { 146 .name = "altera_nios2", 147 .id = UCLASS_CPU, 148 .of_match = altera_nios2_ids, 149 .probe = altera_nios2_probe, 150 .ops = &altera_nios2_ops, 151 .flags = DM_FLAG_PRE_RELOC, 152 }; 153 154 /* This is a dummy function on nios2 */ 155 int dram_init(void) 156 { 157 return 0; 158 } 159