1 /* 2 * (C) Copyright 2004, Psyent Corporation <www.psyent.com> 3 * Scott McNutt <smcnutt@psyent.com> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #include <common.h> 9 #include <cpu.h> 10 #include <dm.h> 11 #include <errno.h> 12 #include <asm/cache.h> 13 14 DECLARE_GLOBAL_DATA_PTR; 15 16 #ifdef CONFIG_DISPLAY_CPUINFO 17 int print_cpuinfo(void) 18 { 19 printf("CPU: Nios-II\n"); 20 return 0; 21 } 22 #endif /* CONFIG_DISPLAY_CPUINFO */ 23 24 #ifdef CONFIG_ALTERA_SYSID 25 int checkboard(void) 26 { 27 display_sysid(); 28 return 0; 29 } 30 #endif 31 32 int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) 33 { 34 disable_interrupts(); 35 /* indirect call to go beyond 256MB limitation of toolchain */ 36 nios2_callr(gd->arch.reset_addr); 37 return 0; 38 } 39 40 /* 41 * COPY EXCEPTION TRAMPOLINE -- copy the tramp to the 42 * exception address. Define CONFIG_ROM_STUBS to prevent 43 * the copy (e.g. exception in flash or in other 44 * softare/firmware component). 45 */ 46 #ifndef CONFIG_ROM_STUBS 47 static void copy_exception_trampoline(void) 48 { 49 extern int _except_start, _except_end; 50 void *except_target = (void *)gd->arch.exception_addr; 51 52 if (&_except_start != except_target) { 53 memcpy(except_target, &_except_start, 54 &_except_end - &_except_start); 55 flush_cache(gd->arch.exception_addr, 56 &_except_end - &_except_start); 57 } 58 } 59 #endif 60 61 int arch_cpu_init_dm(void) 62 { 63 struct udevice *dev; 64 int ret; 65 66 ret = uclass_first_device(UCLASS_CPU, &dev); 67 if (ret) 68 return ret; 69 if (!dev) 70 return -ENODEV; 71 72 gd->ram_size = CONFIG_SYS_SDRAM_SIZE; 73 #ifndef CONFIG_ROM_STUBS 74 copy_exception_trampoline(); 75 #endif 76 77 return 0; 78 } 79 80 static int altera_nios2_get_desc(struct udevice *dev, char *buf, int size) 81 { 82 const char *cpu_name = "Nios-II"; 83 84 if (size < strlen(cpu_name)) 85 return -ENOSPC; 86 strcpy(buf, cpu_name); 87 88 return 0; 89 } 90 91 static int altera_nios2_get_info(struct udevice *dev, struct cpu_info *info) 92 { 93 info->cpu_freq = gd->cpu_clk; 94 info->features = (1 << CPU_FEAT_L1_CACHE) | 95 (gd->arch.has_mmu ? (1 << CPU_FEAT_MMU) : 0); 96 97 return 0; 98 } 99 100 static int altera_nios2_get_count(struct udevice *dev) 101 { 102 return 1; 103 } 104 105 static int altera_nios2_probe(struct udevice *dev) 106 { 107 const void *blob = gd->fdt_blob; 108 int node = dev->of_offset; 109 110 gd->cpu_clk = fdtdec_get_int(blob, node, 111 "clock-frequency", 0); 112 gd->arch.dcache_line_size = fdtdec_get_int(blob, node, 113 "dcache-line-size", 0); 114 gd->arch.icache_line_size = fdtdec_get_int(blob, node, 115 "icache-line-size", 0); 116 gd->arch.dcache_size = fdtdec_get_int(blob, node, 117 "dcache-size", 0); 118 gd->arch.icache_size = fdtdec_get_int(blob, node, 119 "icache-size", 0); 120 gd->arch.reset_addr = fdtdec_get_int(blob, node, 121 "altr,reset-addr", 0); 122 gd->arch.exception_addr = fdtdec_get_int(blob, node, 123 "altr,exception-addr", 0); 124 gd->arch.has_initda = fdtdec_get_int(blob, node, 125 "altr,has-initda", 0); 126 gd->arch.has_mmu = fdtdec_get_int(blob, node, 127 "altr,has-mmu", 0); 128 gd->arch.io_region_base = gd->arch.has_mmu ? 0xe0000000 : 0x80000000; 129 gd->arch.mem_region_base = gd->arch.has_mmu ? 0xc0000000 : 0x00000000; 130 gd->arch.physaddr_mask = gd->arch.has_mmu ? 0x1fffffff : 0x7fffffff; 131 132 return 0; 133 } 134 135 static const struct cpu_ops altera_nios2_ops = { 136 .get_desc = altera_nios2_get_desc, 137 .get_info = altera_nios2_get_info, 138 .get_count = altera_nios2_get_count, 139 }; 140 141 static const struct udevice_id altera_nios2_ids[] = { 142 { .compatible = "altr,nios2-1.0" }, 143 { .compatible = "altr,nios2-1.1" }, 144 { } 145 }; 146 147 U_BOOT_DRIVER(altera_nios2) = { 148 .name = "altera_nios2", 149 .id = UCLASS_CPU, 150 .of_match = altera_nios2_ids, 151 .probe = altera_nios2_probe, 152 .ops = &altera_nios2_ops, 153 .flags = DM_FLAG_PRE_RELOC, 154 }; 155