xref: /openbmc/u-boot/arch/nds32/include/asm/macro.h (revision ad3098f7)
1 /*
2  * include/asm-nds32/macro.h
3  *
4  * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
5  * Copyright (C) 2011 Andes Technology Corporation
6  * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
7  *
8  * SPDX-License-Identifier:	GPL-2.0+
9  */
10 
11 #ifndef __ASM_NDS_MACRO_H
12 #define __ASM_NDS_MACRO_H
13 #ifdef __ASSEMBLY__
14 
15 /*
16  * These macros provide a convenient way to write 8, 16 and 32 bit data
17  * to an "immediate address (address used by periphal)" only.
18  * Registers r4 and r5 are used, any data in these registers are
19  * overwritten by the macros.
20  * The macros are valid for any NDS32 architecture, they do not implement
21  * any memory barriers so caution is recommended when using these when the
22  * caches are enabled or on a multi-core system.
23  */
24 
25 .macro	write32, addr, data
26 	li	$r4, \addr
27 	li	$r5, \data
28 	swi	$r5, [$r4]
29 .endm
30 
31 .macro	write16, addr, data
32 	li	$r4, \addr
33 	li	$r5, \data
34 	shi	$r5, [$r4]
35 .endm
36 
37 .macro	write8, addr, data
38 	li	$r4, \addr
39 	li	$r5, \data
40 	sbi	$r5, [$r4]
41 .endm
42 
43 /*
44  * This macro read a value from a register, then do OR operation
45  * (set bit fields) to the value, and then store it back to the register.
46  * Note: Instruction 'ori' supports immediate value up to 15 bits.
47  */
48 .macro	setbf32, addr, data
49 	li	$r4, \addr
50 	lwi	$r5, [$r4]
51 	li	$r6, \data
52 	or	$r5, $r5, $r6
53 	swi	$r5, [$r4]
54 .endm
55 
56 .macro	setbf15, addr, data
57 	li	$r4, \addr
58 	lwi	$r5, [$r4]
59 	ori	$r5, $r5, \data
60 	swi	$r5, [$r4]
61 .endm
62 
63 /*
64  * This macro generates a loop that can be used for delays in the code.
65  * Register r4 is used, any data in this register is overwritten by the
66  * macro.
67  * The macro is valid for any NDS32 architeture. The actual time spent in the
68  * loop will vary from CPU to CPU though.
69  */
70 
71 .macro	wait_timer, time
72 	li	$r4, \time
73 1:
74 	nop
75 	addi	$r4, $r4, -1
76 	bnez    $r4, 1b
77 .endm
78 
79 #endif /* __ASSEMBLY__ */
80 #endif /* __ASM_ARM_MACRO_H */
81