1 /* 2 * Copyright (C) 2011 Andes Technology Corporation 3 * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com> 4 * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com> 5 * 6 * See file CREDITS for list of people who contributed to this 7 * project. 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of 12 * the License, or (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software 21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 22 * MA 02111-1307 USA 23 */ 24 25 #ifndef _ASM_CACHE_H 26 #define _ASM_CACHE_H 27 28 /* cache */ 29 int icache_status(void); 30 void icache_enable(void); 31 void icache_disable(void); 32 int dcache_status(void); 33 void dcache_enable(void); 34 void dcache_disable(void); 35 36 #define DEFINE_GET_SYS_REG(reg) \ 37 static inline unsigned long GET_##reg(void) \ 38 { \ 39 unsigned long val; \ 40 __asm__ volatile ( \ 41 "mfsr %0, $"#reg : "=&r" (val) : : "memory" \ 42 ); \ 43 return val; \ 44 } 45 46 enum cache_t {ICACHE, DCACHE}; 47 DEFINE_GET_SYS_REG(ICM_CFG); 48 DEFINE_GET_SYS_REG(DCM_CFG); 49 #define ICM_CFG_OFF_ISZ 6 /* I-cache line size */ 50 #define ICM_CFG_MSK_ISZ (0x7UL << ICM_CFG_OFF_ISZ) 51 #define DCM_CFG_OFF_DSZ 6 /* D-cache line size */ 52 #define DCM_CFG_MSK_DSZ (0x7UL << DCM_CFG_OFF_DSZ) 53 54 /* 55 * The current upper bound for NDS32 L1 data cache line sizes is 32 bytes. 56 * We use that value for aligning DMA buffers unless the board config has 57 * specified an alternate cache line size. 58 */ 59 #ifdef CONFIG_SYS_CACHELINE_SIZE 60 #define ARCH_DMA_MINALIGN CONFIG_SYS_CACHELINE_SIZE 61 #else 62 #define ARCH_DMA_MINALIGN 32 63 #endif 64 65 #endif /* _ASM_CACHE_H */ 66