1*1e52fea3SMacpaul Lin /* 2*1e52fea3SMacpaul Lin * Copyright (C) 2011 Andes Technology Corporation 3*1e52fea3SMacpaul Lin * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com> 4*1e52fea3SMacpaul Lin * 5*1e52fea3SMacpaul Lin * This program is free software; you can redistribute it and/or modify 6*1e52fea3SMacpaul Lin * it under the terms of the GNU General Public License as published by 7*1e52fea3SMacpaul Lin * the Free Software Foundation; either version 2 of the License, or 8*1e52fea3SMacpaul Lin * (at your option) any later version. 9*1e52fea3SMacpaul Lin * 10*1e52fea3SMacpaul Lin * This program is distributed in the hope that it will be useful, 11*1e52fea3SMacpaul Lin * but WITHOUT ANY WARRANTY; without even the implied warranty of 12*1e52fea3SMacpaul Lin * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13*1e52fea3SMacpaul Lin * GNU General Public License for more details. 14*1e52fea3SMacpaul Lin * 15*1e52fea3SMacpaul Lin * You should have received a copy of the GNU General Public License 16*1e52fea3SMacpaul Lin * along with this program; if not, write to the Free Software 17*1e52fea3SMacpaul Lin * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 18*1e52fea3SMacpaul Lin */ 19*1e52fea3SMacpaul Lin 20*1e52fea3SMacpaul Lin #ifndef __AG102_H 21*1e52fea3SMacpaul Lin #define __AG102_H 22*1e52fea3SMacpaul Lin 23*1e52fea3SMacpaul Lin /* 24*1e52fea3SMacpaul Lin * Hardware register bases 25*1e52fea3SMacpaul Lin */ 26*1e52fea3SMacpaul Lin 27*1e52fea3SMacpaul Lin /* PCI Controller */ 28*1e52fea3SMacpaul Lin #define CONFIG_FTPCI100_BASE 0x90000000 29*1e52fea3SMacpaul Lin /* LPC Controller */ 30*1e52fea3SMacpaul Lin #define CONFIG_LPC_IO_BASE 0x90100000 31*1e52fea3SMacpaul Lin /* LPC Controller */ 32*1e52fea3SMacpaul Lin #define CONFIG_LPC_BASE 0x90200000 33*1e52fea3SMacpaul Lin 34*1e52fea3SMacpaul Lin /* NDS32 Data Local Memory 01 */ 35*1e52fea3SMacpaul Lin #define CONFIG_NDS_DLM1_BASE 0x90300000 36*1e52fea3SMacpaul Lin /* NDS32 Data Local Memory 02 */ 37*1e52fea3SMacpaul Lin #define CONFIG_NDS_DLM2_BASE 0x90400000 38*1e52fea3SMacpaul Lin 39*1e52fea3SMacpaul Lin /* Synopsys DWC DDR2/1 Controller */ 40*1e52fea3SMacpaul Lin #define CONFIG_DWCDDR21MCTL_BASE 0x90500000 41*1e52fea3SMacpaul Lin /* DMA Controller */ 42*1e52fea3SMacpaul Lin #define CONFIG_FTDMAC020_BASE 0x90600000 43*1e52fea3SMacpaul Lin /* FTIDE020_S IDE (ATA) Controller */ 44*1e52fea3SMacpaul Lin #define CONFIG_FTIDE020S_BASE 0x90700000 45*1e52fea3SMacpaul Lin /* USB OTG Controller */ 46*1e52fea3SMacpaul Lin #define CONFIG_FZOTG266HD0A_BASE 0x90800000 47*1e52fea3SMacpaul Lin /* Andes L2 Cache Controller */ 48*1e52fea3SMacpaul Lin #define CONFIG_NCEL2C100_BASE 0x90900000 49*1e52fea3SMacpaul Lin /* XGI XG22 GPU */ 50*1e52fea3SMacpaul Lin #define CONFIG_XGI_XG22_BASE 0x90A00000 51*1e52fea3SMacpaul Lin /* GMAC Ethernet Controller */ 52*1e52fea3SMacpaul Lin #define CONFIG_FTGMAC100_BASE 0x90B00000 53*1e52fea3SMacpaul Lin /* AHB Controller */ 54*1e52fea3SMacpaul Lin #define CONFIG_FTAHBC020S_BASE 0x90C00000 55*1e52fea3SMacpaul Lin /* AHB-to-APB Bridge Controller */ 56*1e52fea3SMacpaul Lin #define CONFIG_FTAPBBRG020S_01_BASE 0x90D00000 57*1e52fea3SMacpaul Lin /* External AHB2AHB Controller */ 58*1e52fea3SMacpaul Lin #define CONFIG_EXT_AHB2AHB_BASE 0x90E00000 59*1e52fea3SMacpaul Lin /* Andes Multi-core Interrupt Controller */ 60*1e52fea3SMacpaul Lin #define CONFIG_NCEMIC100_BASE 0x90F00000 61*1e52fea3SMacpaul Lin 62*1e52fea3SMacpaul Lin /* 63*1e52fea3SMacpaul Lin * APB Device definitions 64*1e52fea3SMacpaul Lin */ 65*1e52fea3SMacpaul Lin /* Compat Flash Controller */ 66*1e52fea3SMacpaul Lin #define CONFIG_FTCFC010_BASE 0x94000000 67*1e52fea3SMacpaul Lin /* APB - SSP (SPI) (without AC97) Controller */ 68*1e52fea3SMacpaul Lin #define CONFIG_FTSSP010_01_BASE 0x94100000 69*1e52fea3SMacpaul Lin /* UART1 - APB STUART Controller (UART0 in Linux) */ 70*1e52fea3SMacpaul Lin #define CONFIG_FTUART010_01_BASE 0x94200000 71*1e52fea3SMacpaul Lin /* FTSDC010 SD Controller */ 72*1e52fea3SMacpaul Lin #define CONFIG_FTSDC010_BASE 0x94400000 73*1e52fea3SMacpaul Lin /* APB - SSP with HDA/AC97 Controller */ 74*1e52fea3SMacpaul Lin #define CONFIG_FTSSP010_02_BASE 0x94500000 75*1e52fea3SMacpaul Lin /* UART2 - APB STUART Controller (UART1 in Linux) */ 76*1e52fea3SMacpaul Lin #define CONFIG_FTUART010_02_BASE 0x94600000 77*1e52fea3SMacpaul Lin /* PCU Controller */ 78*1e52fea3SMacpaul Lin #define CONFIG_ANDES_PCU_BASE 0x94800000 79*1e52fea3SMacpaul Lin /* FTTMR010 Timer */ 80*1e52fea3SMacpaul Lin #define CONFIG_FTTMR010_BASE 0x94900000 81*1e52fea3SMacpaul Lin /* Watch Dog Controller */ 82*1e52fea3SMacpaul Lin #define CONFIG_FTWDT010_BASE 0x94A00000 83*1e52fea3SMacpaul Lin /* FTRTC010 Real Time Clock */ 84*1e52fea3SMacpaul Lin #define CONFIG_FTRTC010_BASE 0x98B00000 85*1e52fea3SMacpaul Lin /* GPIO Controller */ 86*1e52fea3SMacpaul Lin #define CONFIG_FTGPIO010_BASE 0x94C00000 87*1e52fea3SMacpaul Lin /* I2C Controller */ 88*1e52fea3SMacpaul Lin #define CONFIG_FTIIC010_BASE 0x94E00000 89*1e52fea3SMacpaul Lin /* PWM - Pulse Width Modulator Controller */ 90*1e52fea3SMacpaul Lin #define CONFIG_FTPWM010_BASE 0x94F00000 91*1e52fea3SMacpaul Lin 92*1e52fea3SMacpaul Lin /* Debug LED */ 93*1e52fea3SMacpaul Lin #define CONFIG_DEBUG_LED 0x902FFFFC 94*1e52fea3SMacpaul Lin /* Power Management Unit */ 95*1e52fea3SMacpaul Lin #define CONFIG_FTPMU010_BASE 0x98100000 96*1e52fea3SMacpaul Lin 97*1e52fea3SMacpaul Lin #endif /* __AG102_H */ 98