1/dts-v1/; 2/ { 3 compatible = "nds32 ag101p"; 4 #address-cells = <1>; 5 #size-cells = <1>; 6 interrupt-parent = <&intc>; 7 8 aliases { 9 uart0 = &serial0; 10 ethernet0 = &mac0; 11 } ; 12 13 chosen { 14 /* bootargs = "console=ttyS0,38400n8 earlyprintk=uart8250-32bit,0x99600000 debug bootmem_debug memblock=debug loglevel=7"; */ 15 bootargs = "console=ttyS0,38400n8 earlyprintk=uart8250-32bit,0x99600000 debug loglevel=7"; 16 stdout-path = "uart0:38400n8"; 17 tick-timer = &timer0; 18 }; 19 20 memory@0 { 21 device_type = "memory"; 22 reg = <0x00000000 0x40000000>; 23 }; 24 25 cpus { 26 #address-cells = <1>; 27 #size-cells = <0>; 28 cpu@0 { 29 compatible = "andestech,n13"; 30 reg = <0>; 31 /* FIXME: to fill correct frqeuency */ 32 clock-frequency = <60000000>; 33 }; 34 }; 35 36 intc: interrupt-controller { 37 compatible = "andestech,atnointc010"; 38 #interrupt-cells = <1>; 39 interrupt-controller; 40 }; 41 42 serial0: serial@99600000 { 43 compatible = "andestech,uart16550", "ns16550a"; 44 reg = <0x99600000 0x1000>; 45 interrupts = <7 4>; 46 clock-frequency = <14745600>; 47 reg-shift = <2>; 48 no-loopback-test = <1>; 49 }; 50 51 timer0: timer@98400000 { 52 compatible = "andestech,attmr010"; 53 reg = <0x98400000 0x1000>; 54 interrupts = <19 4>; 55 clock-frequency = <15000000>; 56 }; 57 58 mac0: mac@90900000 { 59 compatible = "andestech,atmac100"; 60 reg = <0x90900000 0x1000>; 61 interrupts = <25 4>; 62 }; 63 64 mmc0: mmc@98e00000 { 65 compatible = "andestech,atsdc010"; 66 max-frequency = <30000000>; 67 fifo-depth = <0x10>; 68 reg = <0x98e00000 0x1000>; 69 interrupts = <5 4>; 70 cap-sd-highspeed; 71 }; 72}; 73