1/dts-v1/; 2/ { 3 compatible = "nds32 ae3xx"; 4 #address-cells = <1>; 5 #size-cells = <1>; 6 interrupt-parent = <&intc>; 7 8 aliases { 9 uart0 = &serial0; 10 ethernet0 = &mac0; 11 } ; 12 13 chosen { 14 /* bootargs = "console=ttyS0,38400n8 earlyprintk=uart8250-32bit,0xf0300000 debug bootmem_debug memblock=debug loglevel=7"; */ 15 bootargs = "console=ttyS0,38400n8 earlyprintk=uart8250-32bit,0xf0300000 debug loglevel=7"; 16 stdout-path = "uart0:38400n8"; 17 tick-timer = &timer0; 18 }; 19 20 memory@0 { 21 device_type = "memory"; 22 reg = <0x00000000 0x40000000>; 23 }; 24 25 cpus { 26 #address-cells = <1>; 27 #size-cells = <0>; 28 cpu@0 { 29 compatible = "andestech,n13"; 30 reg = <0>; 31 /* FIXME: to fill correct frqeuency */ 32 clock-frequency = <60000000>; 33 }; 34 }; 35 36 intc: interrupt-controller { 37 compatible = "andestech,atnointc010"; 38 #interrupt-cells = <1>; 39 interrupt-controller; 40 }; 41 42 serial0: serial@f0300000 { 43 compatible = "andestech,uart16550", "ns16550a"; 44 reg = <0xf0300000 0x1000>; 45 interrupts = <7 4>; 46 clock-frequency = <14745600>; 47 reg-shift = <2>; 48 reg-offset = <32>; 49 no-loopback-test = <1>; 50 }; 51 52 timer0: timer@f0400000 { 53 compatible = "andestech,atcpit100"; 54 reg = <0xf0400000 0x1000>; 55 interrupts = <2 4>; 56 clock-frequency = <30000000>; 57 }; 58 59 mac0: mac@e0100000 { 60 compatible = "andestech,atmac100"; 61 reg = <0xe0100000 0x1000>; 62 interrupts = <25 4>; 63 }; 64 65 nor@0,0 { 66 compatible = "cfi-flash"; 67 reg = <0x88000000 0x1000>; 68 bank-width = <2>; 69 device-width = <1>; 70 }; 71 72}; 73