1*b841b6e9Srick/dts-v1/; 2*b841b6e9Srick/ { 3*b841b6e9Srick compatible = "nds32 ae3xx"; 4*b841b6e9Srick #address-cells = <1>; 5*b841b6e9Srick #size-cells = <1>; 6*b841b6e9Srick interrupt-parent = <&intc>; 7*b841b6e9Srick 8*b841b6e9Srick aliases { 9*b841b6e9Srick uart0 = &serial0; 10*b841b6e9Srick } ; 11*b841b6e9Srick 12*b841b6e9Srick chosen { 13*b841b6e9Srick /* bootargs = "console=ttyS0,38400n8 earlyprintk=uart8250-32bit,0xf0300000 debug bootmem_debug memblock=debug loglevel=7"; */ 14*b841b6e9Srick bootargs = "console=ttyS0,38400n8 earlyprintk=uart8250-32bit,0xf0300000 debug loglevel=7"; 15*b841b6e9Srick stdout-path = "uart0:38400n8"; 16*b841b6e9Srick tick-timer = &timer0; 17*b841b6e9Srick }; 18*b841b6e9Srick 19*b841b6e9Srick memory@0 { 20*b841b6e9Srick device_type = "memory"; 21*b841b6e9Srick reg = <0x00000000 0x40000000>; 22*b841b6e9Srick }; 23*b841b6e9Srick 24*b841b6e9Srick cpus { 25*b841b6e9Srick #address-cells = <1>; 26*b841b6e9Srick #size-cells = <0>; 27*b841b6e9Srick cpu@0 { 28*b841b6e9Srick compatible = "andestech,n13"; 29*b841b6e9Srick reg = <0>; 30*b841b6e9Srick /* FIXME: to fill correct frqeuency */ 31*b841b6e9Srick clock-frequency = <60000000>; 32*b841b6e9Srick }; 33*b841b6e9Srick }; 34*b841b6e9Srick 35*b841b6e9Srick intc: interrupt-controller { 36*b841b6e9Srick compatible = "andestech,atnointc010"; 37*b841b6e9Srick #interrupt-cells = <1>; 38*b841b6e9Srick interrupt-controller; 39*b841b6e9Srick }; 40*b841b6e9Srick 41*b841b6e9Srick serial0: serial@f0300000 { 42*b841b6e9Srick compatible = "andestech,uart16550", "ns16550a"; 43*b841b6e9Srick reg = <0xf0300000 0x1000>; 44*b841b6e9Srick interrupts = <7 4>; 45*b841b6e9Srick clock-frequency = <14745600>; 46*b841b6e9Srick reg-shift = <2>; 47*b841b6e9Srick reg-offset = <32>; 48*b841b6e9Srick no-loopback-test = <1>; 49*b841b6e9Srick }; 50*b841b6e9Srick 51*b841b6e9Srick timer0: timer@f0400000 { 52*b841b6e9Srick compatible = "andestech,atcpit100"; 53*b841b6e9Srick reg = <0xf0400000 0x1000>; 54*b841b6e9Srick interrupts = <2 4>; 55*b841b6e9Srick clock-frequency = <30000000>; 56*b841b6e9Srick }; 57*b841b6e9Srick 58*b841b6e9Srick nor@0,0 { 59*b841b6e9Srick compatible = "cfi-flash"; 60*b841b6e9Srick reg = <0x88000000 0x1000>; 61*b841b6e9Srick bank-width = <2>; 62*b841b6e9Srick device-width = <1>; 63*b841b6e9Srick }; 64*b841b6e9Srick 65*b841b6e9Srick}; 66