1/*
2 * Copyright (C) 2011 Andes Technology Corporation
3 * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
4 * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
5 *
6 * SPDX-License-Identifier:	GPL-2.0+
7 */
8
9.text
10
11#include <common.h>
12#include <config.h>
13
14#include <asm/macro.h>
15#include <generated/asm-offsets.h>
16
17/*
18 * parameters for the SDRAM controller
19 */
20#define SDMC_TP1_A		(CONFIG_FTSDMC021_BASE + FTSDMC021_TP1)
21#define SDMC_TP2_A		(CONFIG_FTSDMC021_BASE + FTSDMC021_TP2)
22#define SDMC_CR1_A		(CONFIG_FTSDMC021_BASE + FTSDMC021_CR1)
23#define SDMC_CR2_A		(CONFIG_FTSDMC021_BASE + FTSDMC021_CR2)
24#define SDMC_B0_BSR_A		(CONFIG_FTSDMC021_BASE + FTSDMC021_BANK0_BSR)
25#define SDMC_B1_BSR_A		(CONFIG_FTSDMC021_BASE + FTSDMC021_BANK1_BSR)
26
27#define SDMC_TP1_D		CONFIG_SYS_FTSDMC021_TP1
28#define SDMC_TP2_D		CONFIG_SYS_FTSDMC021_TP2
29#define SDMC_CR1_D		CONFIG_SYS_FTSDMC021_CR1
30#define SDMC_CR2_D		CONFIG_SYS_FTSDMC021_CR2
31
32#define SDMC_B0_BSR_D		CONFIG_SYS_FTSDMC021_BANK0_BSR
33#define SDMC_B1_BSR_D		CONFIG_SYS_FTSDMC021_BANK1_BSR
34
35/*
36 * parameters for the static memory controller
37 */
38#define SMC_BANK0_CR_A		(CONFIG_FTSMC020_BASE + FTSMC020_BANK0_CR)
39#define SMC_BANK0_TPR_A		(CONFIG_FTSMC020_BASE + FTSMC020_BANK0_TPR)
40
41#define SMC_BANK0_CR_D		FTSMC020_BANK0_LOWLV_CONFIG
42#define SMC_BANK0_TPR_D		FTSMC020_BANK0_LOWLV_TIMING
43
44/*
45 * parameters for the ahbc controller
46 */
47#define AHBC_CR_A		(CONFIG_FTAHBC020S_BASE + FTAHBC020S_CR)
48#define AHBC_BSR6_A	(CONFIG_FTAHBC020S_BASE + FTAHBC020S_SLAVE_BSR_6)
49
50#define AHBC_BSR6_D		CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6
51
52/*
53 * parameters for the pmu controoler
54 */
55#define PMU_PDLLCR0_A		(CONFIG_FTPMU010_BASE + FTPMU010_PDLLCR0)
56
57/*
58 * numeric 7 segment display
59 */
60.macro	led, num
61	write32	CONFIG_DEBUG_LED, \num
62.endm
63
64/*
65 * Waiting for SDRAM to set up
66 */
67.macro	wait_sdram
68	li	$r0, CONFIG_FTSDMC021_BASE
691:
70	lwi	$r1, [$r0+FTSDMC021_CR2]
71	bnez	$r1, 1b
72.endm
73
74#ifndef CONFIG_SKIP_LOWLEVEL_INIT
75.globl	lowlevel_init
76lowlevel_init:
77	move	$r10, $lp
78
79	led	0x0
80	jal	mem_init
81
82	led	0x10
83	jal	remap
84
85#if (defined(NDS32_EXT_FPU_DP) || defined(NDS32_EXT_FPU_SP))
86	led	0x1f
87	jal	enable_fpu
88#endif
89
90	led	0x20
91	ret	$r10
92
93mem_init:
94	move	$r11, $lp
95
96	/*
97	 * mem_init:
98	 *	There are 2 bank connected to FTSMC020 on AG101
99	 *	BANK0: FLASH/ROM (SW5, J16), BANK1: OnBoard SDRAM.
100	 *	we need to set onboard SDRAM before remap and relocation.
101	 */
102	led	0x01
103	write32	SMC_BANK0_CR_A, SMC_BANK0_CR_D			! 0x10000052
104	write32	SMC_BANK0_TPR_A, SMC_BANK0_TPR_D		! 0x00151151
105
106	/*
107	 * config AHB Controller
108	 */
109	led	0x02
110	write32	AHBC_BSR6_A, AHBC_BSR6_D
111
112	/*
113	 * config PMU controller
114	 */
115	/* ftpmu010_dlldis_disable, must do it in lowleve_init */
116	led	0x03
117	setbf32	PMU_PDLLCR0_A, FTPMU010_PDLLCR0_DLLDIS		! 0x00010000
118
119	/*
120	 * config SDRAM controller
121	 */
122	led	0x04
123	write32	SDMC_TP1_A, SDMC_TP1_D				! 0x00011312
124	led	0x05
125	write32	SDMC_TP2_A, SDMC_TP2_D				! 0x00480180
126	led	0x06
127	write32	SDMC_CR1_A, SDMC_CR1_D				! 0x00002326
128
129	led	0x07
130	write32	SDMC_CR2_A, FTSDMC021_CR2_IPREC			! 0x00000010
131	wait_sdram
132
133	led	0x08
134	write32	SDMC_CR2_A, FTSDMC021_CR2_ISMR			! 0x00000004
135	wait_sdram
136
137	led	0x09
138	write32	SDMC_CR2_A, FTSDMC021_CR2_IREF			! 0x00000008
139	wait_sdram
140
141	led	0x0a
142	move	$lp, $r11
143	ret
144
145remap:
146	move	$r11, $lp
147#ifdef __NDS32_N1213_43U1H__	/* NDS32 V0 ISA - AG101 Only */
148	bal	2f
149relo_base:
150	move	$r0, $lp
151#else
152relo_base:
153	mfusr	$r0, $pc
154#endif /* __NDS32_N1213_43U1H__ */
155
156	/*
157	 * Remapping
158	 */
159	led	0x1a
160	write32	SDMC_B0_BSR_A, SDMC_B0_BSR_D		! 0x00001100
161	write32	SDMC_B1_BSR_A, SDMC_B1_BSR_D		! 0x00001140
162
163	/* clear empty BSR registers */
164	led	0x1b
165	li	$r4, CONFIG_FTSDMC021_BASE
166	li	$r5, 0x0
167	swi	$r5, [$r4 + FTSDMC021_BANK2_BSR]
168	swi	$r5, [$r4 + FTSDMC021_BANK3_BSR]
169
170#ifdef CONFIG_MEM_REMAP
171	/*
172	 * Copy ROM code to SDRAM base for memory remap layout.
173	 * This is not the real relocation, the real relocation is the function
174	 * relocate_code() is start.S which supports the systems is memory
175	 * remapped or not.
176	 */
177	/*
178	 * Doing memory remap is essential for preparing some non-OS or RTOS
179	 * applications.
180	 *
181	 * This is also a must on ADP-AG101 board.
182	 * The reason is because the ROM/FLASH circuit on PCB board.
183	 * AG101-A0 board has 2 jumpers MA17 and SW5 to configure which
184	 * ROM/FLASH is used to boot.
185	 *
186	 * When SW5 = "0101", MA17 = LO, the ROM is connected to BANK0,
187	 * and the FLASH is connected to BANK1.
188	 * When SW5 = "1010", MA17 = HI, the ROM is disabled (still at BANK0),
189	 * and the FLASH is connected to BANK0.
190	 * It will occur problem when doing flash probing if the flash is at
191	 * BANK0 (0x00000000) while memory remapping was skipped.
192	 *
193	 * Other board like ADP-AG101P may not enable this since there is only
194	 * a FLASH connected to bank0.
195	 */
196	led	0x11
197	li	$r4, PHYS_SDRAM_0_AT_INIT		/* 0x10000000 */
198	li	$r5, 0x0
199	la	$r1, relo_base				/* get $pc or $lp */
200	sub	$r2, $r0, $r1
201	sethi	$r6, hi20(_end)
202	ori	$r6, $r6, lo12(_end)
203	add	$r6, $r6, $r2
2041:
205	lwi.p	$r7, [$r5], #4
206	swi.p	$r7, [$r4], #4
207	blt	$r5, $r6, 1b
208
209	/* set remap bit */
210	/*
211	 * MEM remap bit is operational
212	 * - use it to map writeable memory at 0x00000000, in place of flash
213	 * - before remap: flash/rom 0x00000000, sdram: 0x10000000-0x4fffffff
214	 * - after  remap: flash/rom 0x80000000, sdram: 0x00000000
215	 */
216	led	0x1c
217	write32 SDMC_B0_BSR_A, 0x00001000
218	write32 SDMC_B1_BSR_A, 0x00001040
219	setbf15	AHBC_CR_A, FTAHBC020S_CR_REMAP		! 0x1
220
221#endif /* #ifdef CONFIG_MEM_REMAP */
222	move	$lp, $r11
2232:
224	ret
225
226	/*
227	 * enable_fpu:
228	 *  Some of Andes CPU version support FPU coprocessor, if so,
229	 *  and toolchain support FPU instruction set, we should enable it.
230	 */
231#if (defined(NDS32_EXT_FPU_DP) || defined(NDS32_EXT_FPU_SP))
232enable_fpu:
233	mfsr    $r0, $CPU_VER     /* enable FPU if it exists */
234	srli    $r0, $r0, 3
235	andi    $r0, $r0, 1
236	beqz    $r0, 1f           /* skip if no COP */
237	mfsr    $r0, $FUCOP_EXIST
238	srli    $r0, $r0, 31
239	beqz    $r0, 1f           /* skip if no FPU */
240	mfsr    $r0, $FUCOP_CTL
241	ori     $r0, $r0, 1
242	mtsr    $r0, $FUCOP_CTL
2431:
244	ret
245#endif
246
247.globl show_led
248show_led:
249    li      $r8, (CONFIG_DEBUG_LED)
250    swi     $r7, [$r8]
251    ret
252#endif /* #ifndef CONFIG_SKIP_LOWLEVEL_INIT */
253