1/* 2 * Copyright (C) 2011 Andes Technology Corporation 3 * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com> 4 * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com> 5 * 6 * See file CREDITS for list of people who contributed to this 7 * project. 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of 12 * the License, or (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software 21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 22 * MA 02111-1307 USA 23 */ 24 25.text 26 27#include <common.h> 28#include <config.h> 29 30#include <asm/macro.h> 31#include <generated/asm-offsets.h> 32 33/* 34 * parameters for the SDRAM controller 35 */ 36#define SDMC_TP1_A (CONFIG_FTSDMC021_BASE + FTSDMC021_TP1) 37#define SDMC_TP2_A (CONFIG_FTSDMC021_BASE + FTSDMC021_TP2) 38#define SDMC_CR1_A (CONFIG_FTSDMC021_BASE + FTSDMC021_CR1) 39#define SDMC_CR2_A (CONFIG_FTSDMC021_BASE + FTSDMC021_CR2) 40#define SDMC_B0_BSR_A (CONFIG_FTSDMC021_BASE + FTSDMC021_BANK0_BSR) 41 42#define SDMC_TP1_D CONFIG_SYS_FTSDMC021_TP1 43#define SDMC_TP2_D CONFIG_SYS_FTSDMC021_TP2 44#define SDMC_CR1_D CONFIG_SYS_FTSDMC021_CR1 45#define SDMC_CR2_D CONFIG_SYS_FTSDMC021_CR2 46 47#define SDMC_B0_BSR_D CONFIG_SYS_FTSDMC021_BANK0_BSR 48 49/* 50 * parameters for the static memory controller 51 */ 52#define SMC_BANK0_CR_A (CONFIG_FTSMC020_BASE + FTSMC020_BANK0_CR) 53#define SMC_BANK0_TPR_A (CONFIG_FTSMC020_BASE + FTSMC020_BANK0_TPR) 54 55#define SMC_BANK0_CR_D FTSMC020_BANK0_LOWLV_CONFIG 56#define SMC_BANK0_TPR_D FTSMC020_BANK0_LOWLV_TIMING 57 58/* 59 * parameters for the ahbc controller 60 */ 61#define AHBC_CR_A (CONFIG_FTAHBC020S_BASE + FTAHBC020S_CR) 62#define AHBC_BSR6_A (CONFIG_FTAHBC020S_BASE + FTAHBC020S_SLAVE_BSR_6) 63 64#define AHBC_BSR6_D CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6 65 66/* 67 * parameters for the pmu controoler 68 */ 69#define PMU_PDLLCR0_A (CONFIG_FTPMU010_BASE + FTPMU010_PDLLCR0) 70 71/* 72 * numeric 7 segment display 73 */ 74.macro led, num 75 write32 CONFIG_DEBUG_LED, \num 76.endm 77 78/* 79 * Waiting for SDRAM to set up 80 */ 81.macro wait_sdram 82 li $r0, CONFIG_FTSDMC021_BASE 831: 84 lwi $r1, [$r0+FTSDMC021_CR2] 85 bnez $r1, 1b 86.endm 87 88#ifndef CONFIG_SKIP_LOWLEVEL_INIT 89.globl lowlevel_init 90lowlevel_init: 91 move $r10, $lp 92 93 led 0x0 94 jal mem_init 95 96 led 0x10 97 jal remap 98 99 led 0x20 100 ret $r10 101 102mem_init: 103 move $r11, $lp 104 105 /* 106 * mem_init: 107 * There are 2 bank connected to FTSMC020 on AG101 108 * BANK0: FLASH/ROM (SW5, J16), BANK1: OnBoard SDRAM. 109 * we need to set onboard SDRAM before remap and relocation. 110 */ 111 led 0x01 112 write32 SMC_BANK0_CR_A, SMC_BANK0_CR_D ! 0x10000052 113 write32 SMC_BANK0_TPR_A, SMC_BANK0_TPR_D ! 0x00151151 114 115 /* 116 * config AHB Controller 117 */ 118 led 0x02 119 write32 AHBC_BSR6_A, AHBC_BSR6_D 120 121 /* 122 * config PMU controller 123 */ 124 /* ftpmu010_dlldis_disable, must do it in lowleve_init */ 125 led 0x03 126 setbf32 PMU_PDLLCR0_A, FTPMU010_PDLLCR0_DLLDIS ! 0x00010000 127 128 /* 129 * config SDRAM controller 130 */ 131 led 0x04 132 write32 SDMC_TP1_A, SDMC_TP1_D ! 0x00011312 133 led 0x05 134 write32 SDMC_TP2_A, SDMC_TP2_D ! 0x00480180 135 led 0x06 136 write32 SDMC_CR1_A, SDMC_CR1_D ! 0x00002326 137 138 led 0x07 139 write32 SDMC_CR2_A, FTSDMC021_CR2_IPREC ! 0x00000010 140 wait_sdram 141 142 led 0x08 143 write32 SDMC_CR2_A, FTSDMC021_CR2_ISMR ! 0x00000004 144 wait_sdram 145 146 led 0x09 147 write32 SDMC_CR2_A, FTSDMC021_CR2_IREF ! 0x00000008 148 wait_sdram 149 150 led 0x0a 151 move $lp, $r11 152 ret 153 154remap: 155 move $r11, $lp 156#ifdef __NDS32_N1213_43U1H__ /* NDS32 V0 ISA - AG101 Only */ 157 bal 2f 158relo_base: 159 move $r0, $lp 160#else 161relo_base: 162 mfusr $r0, $pc 163#endif /* __NDS32_N1213_43U1H__ */ 164 165 /* 166 * Remapping 167 */ 168 led 0x1a 169 write32 SDMC_B0_BSR_A, SDMC_B0_BSR_D ! 0x00001100 170 171 /* clear empty BSR registers */ 172 led 0x1b 173 li $r4, CONFIG_FTSDMC021_BASE 174 li $r5, 0x0 175 swi $r5, [$r4 + FTSDMC021_BANK1_BSR] 176 swi $r5, [$r4 + FTSDMC021_BANK2_BSR] 177 swi $r5, [$r4 + FTSDMC021_BANK3_BSR] 178 179#ifdef CONFIG_MEM_REMAP 180 /* 181 * Copy ROM code to SDRAM base for memory remap layout. 182 * This is not the real relocation, the real relocation is the function 183 * relocate_code() is start.S which supports the systems is memory 184 * remapped or not. 185 */ 186 /* 187 * Doing memory remap is essential for preparing some non-OS or RTOS 188 * applications. 189 * 190 * This is also a must on ADP-AG101 board. 191 * The reason is because the ROM/FLASH circuit on PCB board. 192 * AG101-A0 board has 2 jumpers MA17 and SW5 to configure which 193 * ROM/FLASH is used to boot. 194 * 195 * When SW5 = "0101", MA17 = LO, the ROM is connected to BANK0, 196 * and the FLASH is connected to BANK1. 197 * When SW5 = "1010", MA17 = HI, the ROM is disabled (still at BANK0), 198 * and the FLASH is connected to BANK0. 199 * It will occur problem when doing flash probing if the flash is at 200 * BANK0 (0x00000000) while memory remapping was skipped. 201 * 202 * Other board like ADP-AG101P may not enable this since there is only 203 * a FLASH connected to bank0. 204 */ 205 led 0x11 206 li $r4, PHYS_SDRAM_0_AT_INIT /* 0x10000000 */ 207 li $r5, 0x0 208 la $r1, relo_base /* get $pc or $lp */ 209 sub $r2, $r0, $r1 210 sethi $r6, hi20(_end) 211 ori $r6, $r6, lo12(_end) 212 add $r6, $r6, $r2 2131: 214 lwi.p $r7, [$r5], #4 215 swi.p $r7, [$r4], #4 216 blt $r5, $r6, 1b 217 218 /* set remap bit */ 219 /* 220 * MEM remap bit is operational 221 * - use it to map writeable memory at 0x00000000, in place of flash 222 * - before remap: flash/rom 0x00000000, sdram: 0x10000000-0x4fffffff 223 * - after remap: flash/rom 0x80000000, sdram: 0x00000000 224 */ 225 led 0x1c 226 setbf15 AHBC_CR_A, FTAHBC020S_CR_REMAP ! 0x1 227 228#endif /* #ifdef CONFIG_MEM_REMAP */ 229 move $lp, $r11 2302: 231 ret 232 233.globl show_led 234show_led: 235 li $r8, (CONFIG_DEBUG_LED) 236 swi $r7, [$r8] 237 ret 238#endif /* #ifndef CONFIG_SKIP_LOWLEVEL_INIT */ 239