1/*
2 * Copyright (C) 2011 Andes Technology Corporation
3 * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
4 * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
5 *
6 * SPDX-License-Identifier:	GPL-2.0+
7 */
8
9.text
10
11#include <common.h>
12#include <config.h>
13
14#include <asm/macro.h>
15#include <generated/asm-offsets.h>
16
17/*
18 * parameters for the SDRAM controller
19 */
20#define SDMC_TP1_A		(CONFIG_FTSDMC021_BASE + FTSDMC021_TP1)
21#define SDMC_TP2_A		(CONFIG_FTSDMC021_BASE + FTSDMC021_TP2)
22#define SDMC_CR1_A		(CONFIG_FTSDMC021_BASE + FTSDMC021_CR1)
23#define SDMC_CR2_A		(CONFIG_FTSDMC021_BASE + FTSDMC021_CR2)
24#define SDMC_B0_BSR_A		(CONFIG_FTSDMC021_BASE + FTSDMC021_BANK0_BSR)
25#define SDMC_B1_BSR_A		(CONFIG_FTSDMC021_BASE + FTSDMC021_BANK1_BSR)
26
27#define SDMC_TP1_D		CONFIG_SYS_FTSDMC021_TP1
28#define SDMC_TP2_D		CONFIG_SYS_FTSDMC021_TP2
29#define SDMC_CR1_D		CONFIG_SYS_FTSDMC021_CR1
30#define SDMC_CR2_D		CONFIG_SYS_FTSDMC021_CR2
31
32#define SDMC_B0_BSR_D		CONFIG_SYS_FTSDMC021_BANK0_BSR
33#define SDMC_B1_BSR_D		CONFIG_SYS_FTSDMC021_BANK1_BSR
34
35
36/*
37 * for Orca and Emerald
38 */
39#define BOARD_ID_REG		0x104
40#define BOARD_ID_FAMILY_MASK 	0xfff000
41#define BOARD_ID_FAMILY_V5   	0x556000
42#define BOARD_ID_FAMILY_K7   	0x74b000
43
44/*
45 * parameters for the static memory controller
46 */
47#define SMC_BANK0_CR_A		(CONFIG_FTSMC020_BASE + FTSMC020_BANK0_CR)
48#define SMC_BANK0_TPR_A		(CONFIG_FTSMC020_BASE + FTSMC020_BANK0_TPR)
49
50#define SMC_BANK0_CR_D		FTSMC020_BANK0_LOWLV_CONFIG
51#define SMC_BANK0_TPR_D		FTSMC020_BANK0_LOWLV_TIMING
52
53/*
54 * parameters for the ahbc controller
55 */
56#define AHBC_CR_A		(CONFIG_FTAHBC020S_BASE + FTAHBC020S_CR)
57#define AHBC_BSR6_A	(CONFIG_FTAHBC020S_BASE + FTAHBC020S_SLAVE_BSR_6)
58
59/*
60 * for Orca and Emerald
61 */
62#define AHBC_BSR4_A	(CONFIG_FTAHBC020S_BASE + FTAHBC020S_SLAVE_BSR_4)
63#define AHBC_BSR6_D		CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6
64
65/*
66 * parameters for the pmu controoler
67 */
68#define PMU_PDLLCR0_A		(CONFIG_FTPMU010_BASE + FTPMU010_PDLLCR0)
69
70/*
71 * numeric 7 segment display
72 */
73.macro	led, num
74	write32	CONFIG_DEBUG_LED, \num
75.endm
76
77/*
78 * Waiting for SDRAM to set up
79 */
80.macro	wait_sdram
81	li	$r0, CONFIG_FTSDMC021_BASE
821:
83	lwi	$r1, [$r0+FTSDMC021_CR2]
84	bnez	$r1, 1b
85.endm
86
87#ifndef CONFIG_SKIP_LOWLEVEL_INIT
88.globl	lowlevel_init
89lowlevel_init:
90	move	$r10, $lp
91
92	led	0x0
93	jal	mem_init
94
95	led	0x10
96	jal	remap
97
98#if (defined(NDS32_EXT_FPU_DP) || defined(NDS32_EXT_FPU_SP))
99	led	0x1f
100	jal	enable_fpu
101#endif
102
103	led	0x20
104	ret	$r10
105
106mem_init:
107	move	$r11, $lp
108
109	/*
110	 * mem_init:
111	 *	There are 2 bank connected to FTSMC020 on AG101
112	 *	BANK0: FLASH/ROM (SW5, J16), BANK1: OnBoard SDRAM.
113	 *	we need to set onboard SDRAM before remap and relocation.
114	 */
115	led	0x01
116
117  /*
118   * for Orca and Emerald
119   * disable write protection and reset bank size
120   */
121	li	$r0, SMC_BANK0_CR_A
122	lwi $r1, [$r0+#0x00]
123	ori $r1, $r1, 0x8f0
124	xori $r1, $r1, 0x8f0
125  /*
126   * check board
127   */
128	li      $r3, CONFIG_FTPMU010_BASE + BOARD_ID_REG
129  lwi     $r3, [$r3]
130  li      $r4, BOARD_ID_FAMILY_MASK
131  and     $r3, $r3, $r4
132  li      $r4, BOARD_ID_FAMILY_K7
133  xor     $r4, $r3, $r4
134  beqz    $r4, use_flash_16bit_boot
135  /*
136   * 32-bit mode
137   */
138use_flash_32bit_boot:
139	ori     $r1, $r1, 0x50
140  li      $r2, 0x00151151
141  j       sdram_b0_cr
142  /*
143   * 16-bit mode
144   */
145use_flash_16bit_boot:
146  ori     $r1, $r1, 0x60
147  li      $r2, 0x00153153
148  /*
149   * SRAM bank0 config
150   */
151sdram_b0_cr:
152  swi     $r1, [$r0+#0x00]
153  swi     $r2, [$r0+#0x04]
154
155	/*
156	 * config AHB Controller
157	 */
158	led	0x02
159
160	/*
161	 * config PMU controller
162	 */
163	/* ftpmu010_dlldis_disable, must do it in lowleve_init */
164	led	0x03
165	setbf32	PMU_PDLLCR0_A, FTPMU010_PDLLCR0_DLLDIS		! 0x00010000
166
167	/*
168	 * config SDRAM controller
169	 */
170	led	0x04
171	write32	SDMC_TP1_A, SDMC_TP1_D				! 0x00011312
172	led	0x05
173	write32	SDMC_TP2_A, SDMC_TP2_D				! 0x00480180
174	led	0x06
175	write32	SDMC_CR1_A, SDMC_CR1_D				! 0x00002326
176
177	led	0x07
178	write32	SDMC_CR2_A, FTSDMC021_CR2_IPREC			! 0x00000010
179	wait_sdram
180
181	led	0x08
182	write32	SDMC_CR2_A, FTSDMC021_CR2_ISMR			! 0x00000004
183	wait_sdram
184
185	led	0x09
186	write32	SDMC_CR2_A, FTSDMC021_CR2_IREF			! 0x00000008
187	wait_sdram
188
189	led	0x0a
190	move	$lp, $r11
191	ret
192
193remap:
194	move	$r11, $lp
195#ifdef __NDS32_N1213_43U1H__	/* NDS32 V0 ISA - AG101 Only */
196	bal	2f
197relo_base:
198	move	$r0, $lp
199#else
200relo_base:
201	mfusr	$r0, $pc
202#endif /* __NDS32_N1213_43U1H__ */
203
204	/*
205	 * Remapping
206	 */
207	led	0x1a
208	write32	SDMC_B0_BSR_A, SDMC_B0_BSR_D		! 0x00001100
209	write32	SDMC_B1_BSR_A, SDMC_B1_BSR_D		! 0x00001140
210
211	/* clear empty BSR registers */
212	led	0x1b
213	li	$r4, CONFIG_FTSDMC021_BASE
214	li	$r5, 0x0
215	swi	$r5, [$r4 + FTSDMC021_BANK2_BSR]
216	swi	$r5, [$r4 + FTSDMC021_BANK3_BSR]
217
218#ifdef CONFIG_MEM_REMAP
219	/*
220	 * Copy ROM code to SDRAM base for memory remap layout.
221	 * This is not the real relocation, the real relocation is the function
222	 * relocate_code() is start.S which supports the systems is memory
223	 * remapped or not.
224	 */
225	/*
226	 * Doing memory remap is essential for preparing some non-OS or RTOS
227	 * applications.
228	 *
229	 * This is also a must on ADP-AG101 board.
230	 * The reason is because the ROM/FLASH circuit on PCB board.
231	 * AG101-A0 board has 2 jumpers MA17 and SW5 to configure which
232	 * ROM/FLASH is used to boot.
233	 *
234	 * When SW5 = "0101", MA17 = LO, the ROM is connected to BANK0,
235	 * and the FLASH is connected to BANK1.
236	 * When SW5 = "1010", MA17 = HI, the ROM is disabled (still at BANK0),
237	 * and the FLASH is connected to BANK0.
238	 * It will occur problem when doing flash probing if the flash is at
239	 * BANK0 (0x00000000) while memory remapping was skipped.
240	 *
241	 * Other board like ADP-AG101P may not enable this since there is only
242	 * a FLASH connected to bank0.
243	 */
244	led	0x11
245   /*
246    * for Orca and Emerald
247    * read sdram base address automatically
248    */
249	li	$r5, AHBC_BSR6_A
250	lwi $r8, [$r5]
251	li	$r4, 0xfff00000
252	and $r4, $r4, $r8
253
254
255	li	$r5, 0x0
256	la	$r1, relo_base				/* get $pc or $lp */
257	sub	$r2, $r0, $r1
258	sethi	$r6, hi20(_end)
259	ori	$r6, $r6, lo12(_end)
260	add	$r6, $r6, $r2
2611:
262	lwi.p	$r7, [$r5], #4
263	swi.p	$r7, [$r4], #4
264	blt	$r5, $r6, 1b
265
266	/* set remap bit */
267	/*
268	 * MEM remap bit is operational
269	 * - use it to map writeable memory at 0x00000000, in place of flash
270	 * - before remap: flash/rom 0x00000000, sdram: 0x10000000-0x4fffffff
271	 * - after  remap: flash/rom 0x80000000, sdram: 0x00000000
272	 */
273	led	0x1c
274	write32 SDMC_B0_BSR_A, 0x00001000
275	write32 SDMC_B1_BSR_A, 0x00001040
276	setbf15	AHBC_CR_A, FTAHBC020S_CR_REMAP		! 0x1
277
278  /*
279   * for Orca and Emerald
280   * extend sdram size from 256MB to 2GB
281   */
282	li	$r5, AHBC_BSR6_A
283	lwi $r6, [$r5]
284	li  $r4, 0xfff0ffff
285	and $r6 ,$r4 , $r6
286	li	$r4, 0x000b0000
287	or  $r6, $r4,	$r6
288	swi	$r6, [$r5]
289
290  /*
291   * for Orca and Emerald
292   * extend rom base from 256MB to 2GB
293   */
294	li	$r4, AHBC_BSR4_A
295	lwi $r5, [$r4]
296	li	$r6, 0xffffff
297	and $r5, $r5, $r6
298	li  $r6, 0x80000000
299	or  $r5, $r5, $r6
300	swi $r5,	[$r4]
301#endif /* #ifdef CONFIG_MEM_REMAP */
302	move	$lp, $r11
3032:
304	ret
305
306	/*
307	 * enable_fpu:
308	 *  Some of Andes CPU version support FPU coprocessor, if so,
309	 *  and toolchain support FPU instruction set, we should enable it.
310	 */
311#if (defined(NDS32_EXT_FPU_DP) || defined(NDS32_EXT_FPU_SP))
312enable_fpu:
313	mfsr    $r0, $CPU_VER     /* enable FPU if it exists */
314	srli    $r0, $r0, 3
315	andi    $r0, $r0, 1
316	beqz    $r0, 1f           /* skip if no COP */
317	mfsr    $r0, $FUCOP_EXIST
318	srli    $r0, $r0, 31
319	beqz    $r0, 1f           /* skip if no FPU */
320	mfsr    $r0, $FUCOP_CTL
321	ori     $r0, $r0, 1
322	mtsr    $r0, $FUCOP_CTL
3231:
324	ret
325#endif
326
327.globl show_led
328show_led:
329    li      $r8, (CONFIG_DEBUG_LED)
330    swi     $r7, [$r8]
331    ret
332#endif /* #ifndef CONFIG_SKIP_LOWLEVEL_INIT */
333