1/*
2 * Copyright (C) 2011 Andes Technology Corporation
3 * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
4 * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
5 *
6 * SPDX-License-Identifier:	GPL-2.0+
7 */
8
9.pic
10
11.text
12
13#include <common.h>
14#include <config.h>
15
16#include <asm/macro.h>
17#include <generated/asm-offsets.h>
18
19/*
20 * parameters for the SDRAM controller
21 */
22#define SDMC_TP1_A		(CONFIG_FTSDMC021_BASE + FTSDMC021_TP1)
23#define SDMC_TP2_A		(CONFIG_FTSDMC021_BASE + FTSDMC021_TP2)
24#define SDMC_CR1_A		(CONFIG_FTSDMC021_BASE + FTSDMC021_CR1)
25#define SDMC_CR2_A		(CONFIG_FTSDMC021_BASE + FTSDMC021_CR2)
26#define SDMC_B0_BSR_A		(CONFIG_FTSDMC021_BASE + FTSDMC021_BANK0_BSR)
27#define SDMC_B1_BSR_A		(CONFIG_FTSDMC021_BASE + FTSDMC021_BANK1_BSR)
28
29#define SDMC_TP1_D		CONFIG_SYS_FTSDMC021_TP1
30#define SDMC_TP2_D		CONFIG_SYS_FTSDMC021_TP2
31#define SDMC_CR1_D		CONFIG_SYS_FTSDMC021_CR1
32#define SDMC_CR2_D		CONFIG_SYS_FTSDMC021_CR2
33
34#define SDMC_B0_BSR_D		CONFIG_SYS_FTSDMC021_BANK0_BSR
35#define SDMC_B1_BSR_D		CONFIG_SYS_FTSDMC021_BANK1_BSR
36
37
38/*
39 * for Orca and Emerald
40 */
41#define BOARD_ID_REG		0x104
42#define BOARD_ID_FAMILY_MASK 	0xfff000
43#define BOARD_ID_FAMILY_V5   	0x556000
44#define BOARD_ID_FAMILY_K7   	0x74b000
45
46/*
47 * parameters for the static memory controller
48 */
49#define SMC_BANK0_CR_A		(CONFIG_FTSMC020_BASE + FTSMC020_BANK0_CR)
50#define SMC_BANK0_TPR_A		(CONFIG_FTSMC020_BASE + FTSMC020_BANK0_TPR)
51
52#define SMC_BANK0_CR_D		FTSMC020_BANK0_LOWLV_CONFIG
53#define SMC_BANK0_TPR_D		FTSMC020_BANK0_LOWLV_TIMING
54
55/*
56 * for Orca and Emerald
57 */
58#define AHBC_BSR4_A	(CONFIG_FTAHBC020S_BASE + FTAHBC020S_SLAVE_BSR_4)
59#define AHBC_BSR6_D		CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6
60
61/*
62 * parameters for the pmu controoler
63 */
64#define PMU_PDLLCR0_A		(CONFIG_FTPMU010_BASE + FTPMU010_PDLLCR0)
65
66/*
67 * numeric 7 segment display
68 */
69.macro	led, num
70	write32	CONFIG_DEBUG_LED, \num
71.endm
72
73/*
74 * Waiting for SDRAM to set up
75 */
76.macro	wait_sdram
77	li	$r0, CONFIG_FTSDMC021_BASE
781:
79	lwi	$r1, [$r0+FTSDMC021_CR2]
80	bnez	$r1, 1b
81.endm
82
83.globl	mem_init
84mem_init:
85	move	$r11, $lp
86	li	$r0, SMC_BANK0_CR_A
87	lwi $r1, [$r0+#0x00]
88	ori $r1, $r1, 0x8f0
89	xori $r1, $r1, 0x8f0
90	/* 16-bit mode */
91	ori	  $r1, $r1, 0x60
92	li	  $r2, 0x00153153
93	swi	$r1, [$r0+#0x00]
94	swi	  $r2, [$r0+#0x04]
95	move	  $lp, $r11
96	ret
97
98#ifndef CONFIG_SKIP_LOWLEVEL_INIT
99.globl	lowlevel_init
100lowlevel_init:
101	move	$r10, $lp
102	jal	remap
103
104#if (defined(NDS32_EXT_FPU_DP) || defined(NDS32_EXT_FPU_SP))
105	jal	enable_fpu
106#endif
107	ret	$r10
108
109remap:
110	move	$r11, $lp
111relo_base:
112	mfusr	$r0, $pc
113
114#ifdef CONFIG_MEM_REMAP
115	li	$r4, 0x00000000
116	li	$r5, 0x80000000
117	la  $r6, _end@GOTOFF
1181:
119	lmw.bim	$r12, [$r5], $r19
120	smw.bim	$r12, [$r4], $r19
121	blt	$r5, $r6, 1b
122#endif /* #ifdef CONFIG_MEM_REMAP */
123	move $lp, $r11
1242:
125	ret
126
127	/*
128	 * enable_fpu:
129	 *  Some of Andes CPU version support FPU coprocessor, if so,
130	 *  and toolchain support FPU instruction set, we should enable it.
131	 */
132#if (defined(NDS32_EXT_FPU_DP) || defined(NDS32_EXT_FPU_SP))
133enable_fpu:
134	mfsr    $r0, $CPU_VER     /* enable FPU if it exists */
135	srli    $r0, $r0, 3
136	andi    $r0, $r0, 1
137	beqz    $r0, 1f           /* skip if no COP */
138	mfsr    $r0, $FUCOP_EXIST
139	srli    $r0, $r0, 31
140	beqz    $r0, 1f           /* skip if no FPU */
141	mfsr    $r0, $FUCOP_CTL
142	ori     $r0, $r0, 1
143	mtsr    $r0, $FUCOP_CTL
1441:
145	ret
146#endif
147
148#endif /* #ifndef CONFIG_SKIP_LOWLEVEL_INIT */
149