1 /* 2 * (c) 2015 Paul Thacker <paul.thacker@microchip.com> 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 * 6 */ 7 8 #ifndef __PIC32_REGS_H__ 9 #define __PIC32_REGS_H__ 10 11 #include <asm/io.h> 12 13 /* System Configuration */ 14 #define PIC32_CFG_BASE 0x1f800000 15 16 /* System config register offsets */ 17 #define CFGCON 0x0000 18 #define DEVID 0x0020 19 #define SYSKEY 0x0030 20 #define PMD1 0x0040 21 #define PMD7 0x00a0 22 #define CFGEBIA 0x00c0 23 #define CFGEBIC 0x00d0 24 #define CFGPG 0x00e0 25 #define CFGMPLL 0x0100 26 27 /* Non Volatile Memory (NOR flash) */ 28 #define PIC32_NVM_BASE (PIC32_CFG_BASE + 0x0600) 29 /* Oscillator Configuration */ 30 #define PIC32_OSC_BASE (PIC32_CFG_BASE + 0x1200) 31 /* Peripheral Pin Select Input */ 32 #define PPS_IN_BASE 0x1f801400 33 /* Peripheral Pin Select Output */ 34 #define PPS_OUT_BASE 0x1f801500 35 /* Pin Config */ 36 #define PINCTRL_BASE 0x1f860000 37 38 /* USB Core */ 39 #define PIC32_USB_CORE_BASE 0x1f8e3000 40 #define PIC32_USB_CTRL_BASE 0x1f884000 41 42 /* SPI1-SPI6 */ 43 #define PIC32_SPI1_BASE 0x1f821000 44 45 /* Prefetch Module */ 46 #define PREFETCH_BASE 0x1f8e0000 47 48 /* DDR2 Controller */ 49 #define PIC32_DDR2C_BASE 0x1f8e8000 50 51 /* DDR2 PHY */ 52 #define PIC32_DDR2P_BASE 0x1f8e9100 53 54 /* EBI */ 55 #define PIC32_EBI_BASE 0x1f8e1000 56 57 /* SQI */ 58 #define PIC32_SQI_BASE 0x1f8e2000 59 60 struct pic32_reg_atomic { 61 u32 raw; 62 u32 clr; 63 u32 set; 64 u32 inv; 65 }; 66 67 #define _CLR_OFFSET 0x04 68 #define _SET_OFFSET 0x08 69 #define _INV_OFFSET 0x0c 70 71 static inline void __iomem *pic32_get_syscfg_base(void) 72 { 73 return (void __iomem *)CKSEG1ADDR(PIC32_CFG_BASE); 74 } 75 76 /* Core */ 77 const char *get_core_name(void); 78 79 #endif /* __PIC32_REGS_H__ */ 80