1*4c835a60SStefan Roese /* SPDX-License-Identifier: GPL-2.0+ */ 2*4c835a60SStefan Roese /* 3*4c835a60SStefan Roese * Copyright (C) 2018 Stefan Roese <sr@denx.de> 4*4c835a60SStefan Roese */ 5*4c835a60SStefan Roese 6*4c835a60SStefan Roese #ifndef __MT76XX_H 7*4c835a60SStefan Roese #define __MT76XX_H 8*4c835a60SStefan Roese 9*4c835a60SStefan Roese #define MT76XX_SYSCTL_BASE 0x10000000 10*4c835a60SStefan Roese 11*4c835a60SStefan Roese #define MT76XX_CHIPID_OFFS 0x00 12*4c835a60SStefan Roese #define MT76XX_CHIP_REV_ID_OFFS 0x0c 13*4c835a60SStefan Roese #define MT76XX_SYSCFG0_OFFS 0x10 14*4c835a60SStefan Roese 15*4c835a60SStefan Roese #define MT76XX_MEMCTRL_BASE (MT76XX_SYSCTL_BASE + 0x0300) 16*4c835a60SStefan Roese #define MT76XX_RGCTRL_BASE (MT76XX_SYSCTL_BASE + 0x1000) 17*4c835a60SStefan Roese 18*4c835a60SStefan Roese #define MT76XX_ROM_STATUS_REG (MT76XX_SYSCTL_BASE + 0x0028) 19*4c835a60SStefan Roese #define MT76XX_CLKCFG0_REG (MT76XX_SYSCTL_BASE + 0x002c) 20*4c835a60SStefan Roese #define MT76XX_DYN_CFG0_REG (MT76XX_SYSCTL_BASE + 0x0440) 21*4c835a60SStefan Roese 22*4c835a60SStefan Roese #define DDR_CFG1_REG (MT76XX_MEMCTRL_BASE + 0x44) 23*4c835a60SStefan Roese #define DDR_CFG2_REG (MT76XX_MEMCTRL_BASE + 0x48) 24*4c835a60SStefan Roese #define DDR_CFG3_REG (MT76XX_MEMCTRL_BASE + 0x4c) 25*4c835a60SStefan Roese #define DDR_CFG4_REG (MT76XX_MEMCTRL_BASE + 0x50) 26*4c835a60SStefan Roese 27*4c835a60SStefan Roese #ifndef __ASSEMBLY__ 28*4c835a60SStefan Roese /* Prototypes */ 29*4c835a60SStefan Roese void ddr_calibrate(void); 30*4c835a60SStefan Roese #endif 31*4c835a60SStefan Roese 32*4c835a60SStefan Roese #endif 33