1/* SPDX-License-Identifier: GPL-2.0+ */
2/*
3 * (c) 2018 Stefan Roese <sr@denx.de>
4 *
5 * This code is mostly based on the code extracted from this MediaTek
6 * github repository:
7 *
8 * https://github.com/MediaTek-Labs/linkit-smart-uboot.git
9 *
10 * I was not able to find a specific license or other developers
11 * copyrights here, so I can't add them here.
12 */
13
14#include <config.h>
15#include <asm/regdef.h>
16#include <asm/mipsregs.h>
17#include <asm/addrspace.h>
18#include <asm/asm.h>
19#include "mt76xx.h"
20
21#ifndef BIT
22#define BIT(nr)			(1 << (nr))
23#endif
24
25#define DELAY_USEC(us)		((us) / 100)
26
27#define DDR_CFG1_CHIP_WIDTH_MASK (0x3 << 16)
28#define DDR_CFG1_BUS_WIDTH_MASK	(0x3 << 12)
29
30#if defined(CONFIG_ONBOARD_DDR2_SIZE_256MBIT)
31#define DDR_CFG1_SIZE_VAL	0x222e2323
32#define DDR_CFG4_SIZE_VAL	7
33#endif
34#if defined(CONFIG_ONBOARD_DDR2_SIZE_512MBIT)
35#define DDR_CFG1_SIZE_VAL	0x22322323
36#define DDR_CFG4_SIZE_VAL	9
37#endif
38#if defined(CONFIG_ONBOARD_DDR2_SIZE_1024MBIT)
39#define DDR_CFG1_SIZE_VAL	0x22362323
40#define DDR_CFG4_SIZE_VAL	9
41#endif
42#if defined(CONFIG_ONBOARD_DDR2_SIZE_2048MBIT)
43#define DDR_CFG1_SIZE_VAL	0x223a2323
44#define DDR_CFG4_SIZE_VAL	9
45#endif
46
47#if defined(CONFIG_ONBOARD_DDR2_CHIP_WIDTH_8BIT)
48#define DDR_CFG1_CHIP_WIDTH_VAL	(0x1 << 16)
49#endif
50#if defined(CONFIG_ONBOARD_DDR2_CHIP_WIDTH_16BIT)
51#define DDR_CFG1_CHIP_WIDTH_VAL	(0x2 << 16)
52#endif
53
54#if defined(CONFIG_ONBOARD_DDR2_BUS_WIDTH_16BIT)
55#define DDR_CFG1_BUS_WIDTH_VAL	(0x2 << 12)
56#endif
57#if defined(CONFIG_ONBOARD_DDR2_BUS_WIDTH_32BIT)
58#define DDR_CFG1_BUS_WIDTH_VAL	(0x3 << 12)
59#endif
60
61	.set noreorder
62
63LEAF(lowlevel_init)
64
65	/* Load base addresses as physical addresses for later usage */
66	li	s0, CKSEG1ADDR(MT76XX_SYSCTL_BASE)
67	li	s1, CKSEG1ADDR(MT76XX_MEMCTRL_BASE)
68	li	s2, CKSEG1ADDR(MT76XX_RGCTRL_BASE)
69
70	/* polling CPLL is ready */
71	li	t1, DELAY_USEC(1000000)
72	la	t5, MT76XX_ROM_STATUS_REG
731:
74	lw	t2, 0(t5)
75	andi	t2, t2, 0x1
76	bnez	t2, CPLL_READY
77	subu	t1, t1, 1
78	bgtz	t1, 1b
79	nop
80	la      t0, MT76XX_CLKCFG0_REG
81	lw      t3, 0(t0)
82	ori	t3, t3, 0x1
83	sw	t3, 0(t0)
84	b	CPLL_DONE
85	nop
86CPLL_READY:
87	la	t0, MT76XX_CLKCFG0_REG
88	lw	t1, 0(t0)
89	li	t2, ~0x0c
90	and	t1, t1, t2
91	ori	t1, t1, 0xc
92	sw	t1, 0(t0)
93	la	t0, MT76XX_DYN_CFG0_REG
94	lw	t3, 0(t0)
95	li	t5, ~((0x0f << 8) | (0x0f << 0))
96	and	t3, t3, t5
97	li	t5, (10 << 8) | (1 << 0)
98	or	t3, t3, t5
99	sw	t3, 0(t0)
100	la	t0, MT76XX_CLKCFG0_REG
101	lw	t3, 0(t0)
102	li	t4, ~0x0F
103	and     t3, t3, t4
104	ori	t3, t3, 0xc
105	sw	t3, 0(t0)
106	lw	t3, 0(t0)
107	ori	t3, t3, 0x08
108	sw	t3, 0(t0)
109
110CPLL_DONE:
111	/*
112	 * SDR and DDR initialization: delay 200us
113	 */
114	li	t0, DELAY_USEC(200 + 40)
115	li	t1, 0x1
1161:
117	sub	t0, t0, t1
118	bnez	t0, 1b
119	nop
120
121	/* set DRAM IO PAD for MT7628IC */
122	/* DDR LDO Enable  */
123	lw	t4, 0x100(s2)
124	li	t2, BIT(31)
125	or	t4, t4, t2
126	sw	t4, 0x100(s2)
127	lw	t4, 0x10c(s2)
128	j	LDO_1P8V
129	nop
130LDO_1P8V:
131	li	t2, ~BIT(6)
132	and	t4, t4, t2
133	sw	t4, 0x10c(s2)
134	j	DDRLDO_SOFT_START
135LDO_2P5V:
136	/* suppose external DDR1 LDO 2.5V */
137	li	t2, BIT(6)
138	or	t4, t4, t2
139	sw	t4, 0x10c(s2)
140
141DDRLDO_SOFT_START:
142	lw	t2, 0x10c(s2)
143	li	t3, BIT(16)
144	or	t2, t2, t3
145	sw	t2, 0x10c(s2)
146	li	t3, DELAY_USEC(250*50)
147LDO_DELAY:
148	subu	t3, t3, 1
149	bnez	t3, LDO_DELAY
150	nop
151
152	lw	t2, 0x10c(s2)
153	li	t3, BIT(18)
154	or	t2, t2, t3
155	sw	t2, 0x10c(s2)
156
157SET_RG_BUCK_FPWM:
158	lw	t2, 0x104(s2)
159	ori	t2, t2, BIT(10)
160	sw	t2, 0x104(s2)
161
162DDR_PAD_CFG:
163	/* clean CLK PAD */
164	lw	t2, 0x704(s2)
165	li	t8, 0xfffff0f0
166	and	t2, t2, t8
167	/* clean CMD PAD */
168	lw	t3, 0x70c(s2)
169	li	t8, 0xfffff0f0
170	and	t3, t3, t8
171	/* clean DQ IPAD */
172	lw	t4, 0x710(s2)
173	li	t8, 0xfffff8ff
174	and	t4, t4, t8
175	/* clean DQ OPAD */
176	lw	t5, 0x714(s2)
177	li	t8, 0xfffff0f0
178	and	t5, t5, t8
179	/* clean DQS IPAD */
180	lw	t6, 0x718(s2)
181	li	t8, 0xfffff8ff
182	and	t6, t6, t8
183	/* clean DQS OPAD */
184	lw	t7, 0x71c(s2)
185	li	t8, 0xfffff0f0
186	and	t7, t7, t8
187
188	lw	t9, 0xc(s0)
189	srl	t9, t9, 16
190	andi	t9, t9, 0x1
191	bnez	t9, MT7628_AN_DDR1_PAD
192MT7628_KN_PAD:
193	li	t8, 0x00000303
194	or	t2, t2, t8
195	or	t3, t3, t8
196	or	t5, t5, t8
197	or	t7, t7, t8
198	li	t8, 0x00000000
199	or	t4, t4, t8
200	or	t6, t6, t8
201	j	SET_PAD_CFG
202MT7628_AN_DDR1_PAD:
203	lw	t1, 0x10(s0)
204	andi	t1, t1, 0x1
205	beqz	t1, MT7628_AN_DDR2_PAD
206	li	t8, 0x00000c0c
207	or	t2, t2, t8
208	li	t8, 0x00000202
209	or	t3, t3, t8
210	li	t8, 0x00000707
211	or	t5, t5, t8
212	li	t8, 0x00000c0c
213	or	t7, t7, t8
214	li	t8, 0x00000000
215	or	t4, t4, t8
216	or	t6, t6, t8
217	j	SET_PAD_CFG
218MT7628_AN_DDR2_PAD:
219	li	t8, 0x00000c0c
220	or	t2, t2, t8
221	li	t8, 0x00000202
222	or	t3, t3, t8
223	li	t8, 0x00000404
224	or	t5, t5, t8
225	li	t8, 0x00000c0c
226	or	t7, t7, t8
227	li	t8, 0x00000000		/* ODT off */
228	or	t4, t4, t8
229	or	t6, t6, t8
230
231SET_PAD_CFG:
232	sw	t2, 0x704(s2)
233	sw	t3, 0x70c(s2)
234	sw	t4, 0x710(s2)
235	sw	t5, 0x714(s2)
236	sw	t6, 0x718(s2)
237	sw	t7, 0x71c(s2)
238
239	/*
240	 * DDR initialization: reset pin to 0
241	 */
242	lw	t2, 0x34(s0)
243	and	t2, ~BIT(10)
244	sw	t2, 0x34(s0)
245	nop
246
247	/*
248	 * DDR initialization: wait til reg DDR_CFG1 bit 21 equal to 1 (ready)
249	 */
250DDR_READY:
251	li	t1, DDR_CFG1_REG
252	lw	t0, 0(t1)
253	nop
254	and	t2, t0, BIT(21)
255	beqz	t2, DDR_READY
256	nop
257
258	/*
259	 * DDR initialization
260	 *
261	 * Only DDR2 supported right now. DDR2 support can be added, once
262	 * boards using it will get added to mainline U-Boot.
263	 */
264	li	t1, DDR_CFG2_REG
265	lw	t0, 0(t1)
266	nop
267	and	t0, ~BIT(30)
268	and	t0, ~(7 << 4)
269	or	t0, (4 << 4)
270	or	t0, BIT(30)
271	or	t0, BIT(11)
272	sw	t0, 0(t1)
273	nop
274
275	li	t1, DDR_CFG3_REG
276	lw	t2, 0(t1)
277	/* Disable ODT; reference board ok, ev board fail */
278	and	t2, ~BIT(6)
279	or	t2, BIT(2)
280	li	t0, DDR_CFG4_REG
281	lw	t1, 0(t0)
282	li	t2, ~(0x01f | 0x0f0)
283	and	t1, t1, t2
284	ori	t1, t1, DDR_CFG4_SIZE_VAL
285	sw	t1, 0(t0)
286	nop
287
288	/*
289	 * DDR initialization: config size and width on reg DDR_CFG1
290	 */
291	li	t6, DDR_CFG1_SIZE_VAL
292
293	and	t6, ~DDR_CFG1_CHIP_WIDTH_MASK
294	or	t6, DDR_CFG1_CHIP_WIDTH_VAL
295
296	/* CONFIG DDR_CFG1[13:12] about TOTAL WIDTH */
297	and	t6, ~DDR_CFG1_BUS_WIDTH_MASK
298	or	t6, DDR_CFG1_BUS_WIDTH_VAL
299
300	li	t5, DDR_CFG1_REG
301	sw	t6, 0(t5)
302	nop
303
304	/*
305	 * DDR: enable self auto refresh for power saving
306	 * enable it by default for both RAM and ROM version (for CoC)
307	 */
308	lw	t1, 0x14(s1)
309	nop
310	and	t1, 0xff000000
311	or	t1, 0x01
312	sw	t1, 0x14(s1)
313	nop
314	lw	t1, 0x10(s1)
315	nop
316	or	t1, 0x10
317	sw	t1, 0x10(s1)
318	nop
319
320	jr	ra
321	nop
322	END(lowlevel_init)
323