1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright (C) 2018 Stefan Roese <sr@denx.de> 4 */ 5 6 #include <common.h> 7 #include <dm.h> 8 #include <ram.h> 9 #include <asm/io.h> 10 #include <linux/io.h> 11 #include <linux/sizes.h> 12 #include "mt76xx.h" 13 14 #define STR_LEN 6 15 16 #ifdef CONFIG_BOOT_ROM 17 int mach_cpu_init(void) 18 { 19 ddr_calibrate(); 20 21 return 0; 22 } 23 #endif 24 25 int dram_init(void) 26 { 27 gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, SZ_256M); 28 29 return 0; 30 } 31 32 int print_cpuinfo(void) 33 { 34 static const char * const boot_str[] = { "PLL (3-Byte SPI Addr)", 35 "PLL (4-Byte SPI Addr)", 36 "XTAL (3-Byte SPI Addr)", 37 "XTAL (4-Byte SPI Addr)" }; 38 const void *blob = gd->fdt_blob; 39 void __iomem *sysc_base; 40 char buf[STR_LEN + 1]; 41 fdt_addr_t base; 42 fdt_size_t size; 43 char *str; 44 int node; 45 u32 val; 46 47 /* Get system controller base address */ 48 node = fdt_node_offset_by_compatible(blob, -1, "ralink,mt7620a-sysc"); 49 if (node < 0) 50 return -FDT_ERR_NOTFOUND; 51 52 base = fdtdec_get_addr_size_auto_noparent(blob, node, "reg", 53 0, &size, true); 54 if (base == FDT_ADDR_T_NONE) 55 return -EINVAL; 56 57 sysc_base = ioremap_nocache(base, size); 58 59 str = (char *)sysc_base + MT76XX_CHIPID_OFFS; 60 snprintf(buf, STR_LEN + 1, "%s", str); 61 val = readl(sysc_base + MT76XX_CHIP_REV_ID_OFFS); 62 printf("CPU: %-*s Rev %ld.%ld - ", STR_LEN, buf, 63 (val & GENMASK(11, 8)) >> 8, val & GENMASK(3, 0)); 64 65 val = (readl(sysc_base + MT76XX_SYSCFG0_OFFS) & GENMASK(3, 1)) >> 1; 66 printf("Boot from %s\n", boot_str[val]); 67 68 return 0; 69 } 70