1*6bd8231aSGregory CLEMENT/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ 2*6bd8231aSGregory CLEMENT/* 3*6bd8231aSGregory CLEMENT * Copyright (c) 2018 Microsemi Corporation 4*6bd8231aSGregory CLEMENT */ 5*6bd8231aSGregory CLEMENT 6*6bd8231aSGregory CLEMENT#include <asm/asm.h> 7*6bd8231aSGregory CLEMENT#include <asm/regdef.h> 8*6bd8231aSGregory CLEMENT 9*6bd8231aSGregory CLEMENT#define BASE_MACRO 0x600a0000 10*6bd8231aSGregory CLEMENT#define REG_OFFSET(t, o) (t + (o*4)) 11*6bd8231aSGregory CLEMENT#define REG_MACRO(x) REG_OFFSET(BASE_MACRO, x) 12*6bd8231aSGregory CLEMENT#define BIT(nr) (1 << (nr)) 13*6bd8231aSGregory CLEMENT 14*6bd8231aSGregory CLEMENT#define MACRO_CTRL_PLL5G_STATUS_PLL5G_STATUS0 REG_MACRO(6) 15*6bd8231aSGregory CLEMENT#define MACRO_CTRL_PLL5G_STATUS_PLL5G_STATUS0_LOCK_STATUS BIT(0) 16*6bd8231aSGregory CLEMENT#define MACRO_CTRL_PLL5G_CFG_PLL5G_CFG2 REG_MACRO(2) 17*6bd8231aSGregory CLEMENT#define MACRO_CTRL_PLL5G_CFG_PLL5G_CFG0 REG_MACRO(0) 18*6bd8231aSGregory CLEMENT#define MACRO_CTRL_PLL5G_CFG_PLL5G_CFG0_CPU_CLK_DIV (0x3F << 6) 19*6bd8231aSGregory CLEMENT#define MACRO_CTRL_PLL5G_CFG_PLL5G_CFG0_CPU_CLK_DIV_ENC(x) (x << 6) 20*6bd8231aSGregory CLEMENT 21*6bd8231aSGregory CLEMENT .set noreorder 22*6bd8231aSGregory CLEMENTLEAF(pll_init) 23*6bd8231aSGregory CLEMENT /* Make sure PLL is locked */ 24*6bd8231aSGregory CLEMENT lw v0, MACRO_CTRL_PLL5G_STATUS_PLL5G_STATUS0 25*6bd8231aSGregory CLEMENT andi v1, v0, MACRO_CTRL_PLL5G_STATUS_PLL5G_STATUS0_LOCK_STATUS 26*6bd8231aSGregory CLEMENT bne v1, zero, 1f 27*6bd8231aSGregory CLEMENT nop 28*6bd8231aSGregory CLEMENT 29*6bd8231aSGregory CLEMENT /* Black magic from frontend */ 30*6bd8231aSGregory CLEMENT li v1, 0x00610400 31*6bd8231aSGregory CLEMENT sw v1, MACRO_CTRL_PLL5G_CFG_PLL5G_CFG2 32*6bd8231aSGregory CLEMENT 33*6bd8231aSGregory CLEMENT li v1, 0x00610c00 34*6bd8231aSGregory CLEMENT sw v1, MACRO_CTRL_PLL5G_CFG_PLL5G_CFG2 35*6bd8231aSGregory CLEMENT 36*6bd8231aSGregory CLEMENT li v1, 0x00610800 37*6bd8231aSGregory CLEMENT sw v1, MACRO_CTRL_PLL5G_CFG_PLL5G_CFG2 38*6bd8231aSGregory CLEMENT 39*6bd8231aSGregory CLEMENT li v1, 0x00610000 40*6bd8231aSGregory CLEMENT sw v1, MACRO_CTRL_PLL5G_CFG_PLL5G_CFG2 41*6bd8231aSGregory CLEMENT 42*6bd8231aSGregory CLEMENT /* Wait for lock */ 43*6bd8231aSGregory CLEMENT2: lw v0, MACRO_CTRL_PLL5G_STATUS_PLL5G_STATUS0 44*6bd8231aSGregory CLEMENT andi v1, v0, MACRO_CTRL_PLL5G_STATUS_PLL5G_STATUS0_LOCK_STATUS 45*6bd8231aSGregory CLEMENT /* Keep looping if zero (no lock bit yet) */ 46*6bd8231aSGregory CLEMENT beq v1, zero, 2b 47*6bd8231aSGregory CLEMENT nop 48*6bd8231aSGregory CLEMENT 49*6bd8231aSGregory CLEMENT /* Setup PLL CPU clock divider for 416MHz */ 50*6bd8231aSGregory CLEMENT1: lw v0, MACRO_CTRL_PLL5G_CFG_PLL5G_CFG0 51*6bd8231aSGregory CLEMENT 52*6bd8231aSGregory CLEMENT /* Keep reserved bits */ 53*6bd8231aSGregory CLEMENT li v1, ~MACRO_CTRL_PLL5G_CFG_PLL5G_CFG0_CPU_CLK_DIV 54*6bd8231aSGregory CLEMENT and v0, v0, v1 55*6bd8231aSGregory CLEMENT 56*6bd8231aSGregory CLEMENT /* Set code 6 ~ 416.66 MHz */ 57*6bd8231aSGregory CLEMENT ori v0, v0, MACRO_CTRL_PLL5G_CFG_PLL5G_CFG0_CPU_CLK_DIV_ENC(6) 58*6bd8231aSGregory CLEMENT 59*6bd8231aSGregory CLEMENT sw v0, MACRO_CTRL_PLL5G_CFG_PLL5G_CFG0 60*6bd8231aSGregory CLEMENT jr ra 61*6bd8231aSGregory CLEMENT nop 62*6bd8231aSGregory CLEMENT END(pll_init) 63