1 /* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ 2 /* 3 * Copyright (c) 2018 Microsemi Corporation 4 */ 5 6 #ifndef __ASM_MACH_TLB_H 7 #define __ASM_MACH_TLB_H 8 9 #include <asm/mipsregs.h> 10 #include <mach/common.h> 11 #include <linux/sizes.h> 12 13 #define TLB_HI_MASK 0xffffe000 14 #define TLB_LO_MASK 0x3fffffff /* Masks off Fill bits */ 15 #define TLB_LO_SHIFT 6 /* PFN Start bit */ 16 17 #define PAGEMASK_SHIFT 13 18 19 #define MMU_PAGE_CACHED (3 << 3) /* C(5:3) Cache Coherency Attributes */ 20 #define MMU_PAGE_UNCACHED (2 << 3) /* C(5:3) Cache Coherency Attributes */ 21 #define MMU_PAGE_DIRTY BIT(2) /* = Writeable */ 22 #define MMU_PAGE_VALID BIT(1) 23 #define MMU_PAGE_GLOBAL BIT(0) 24 #define MMU_REGIO_RO_C (MMU_PAGE_CACHED | MMU_PAGE_VALID | MMU_PAGE_GLOBAL) 25 #define MMU_REGIO_RO (MMU_PAGE_UNCACHED | MMU_PAGE_VALID | MMU_PAGE_GLOBAL) 26 #define MMU_REGIO_RW (MMU_PAGE_DIRTY | MMU_REGIO_RO) 27 #define MMU_REGIO_INVAL (MMU_PAGE_GLOBAL) 28 29 #define TLB_COUNT_MASK GENMASK(5, 0) 30 #define TLB_COUNT_OFF 25 31 32 static inline u32 get_tlb_count(void) 33 { 34 register u32 config1; 35 36 config1 = read_c0_config1(); 37 config1 >>= TLB_COUNT_OFF; 38 config1 &= TLB_COUNT_MASK; 39 40 return 1 + config1; 41 } 42 43 static inline void create_tlb(int index, u32 offset, u32 size, u32 tlb_attrib1, 44 u32 tlb_attrib2) 45 { 46 register u32 tlb_mask, tlb_lo0, tlb_lo1; 47 48 tlb_mask = ((size >> 12) - 1) << PAGEMASK_SHIFT; 49 tlb_lo0 = tlb_attrib1 | (offset >> TLB_LO_SHIFT); 50 tlb_lo1 = tlb_attrib2 | ((offset + size) >> TLB_LO_SHIFT); 51 52 write_one_tlb(index, tlb_mask, offset & TLB_HI_MASK, 53 tlb_lo0 & TLB_LO_MASK, tlb_lo1 & TLB_LO_MASK); 54 } 55 #endif /* __ASM_MACH_TLB_H */ 56