1 /* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
2 /*
3  * Copyright (c) 2018 Microsemi Corporation
4  */
5 
6 #ifndef _MSCC_SERVAL_ICPU_CFG_H_
7 #define _MSCC_SERVAL_ICPU_CFG_H_
8 
9 #define ICPU_GPR(x)                                       (0x4 * (x))
10 #define ICPU_GPR_RSZ                                      0x8
11 
12 #define ICPU_RESET                                        0x20
13 
14 #define ICPU_RESET_CORE_RST_CPU_ONLY                      BIT(3)
15 #define ICPU_RESET_CORE_RST_PROTECT                       BIT(2)
16 #define ICPU_RESET_CORE_RST_FORCE                         BIT(1)
17 #define ICPU_RESET_MEM_RST_FORCE                          BIT(0)
18 
19 #define ICPU_GENERAL_CTRL                                 0x24
20 
21 #define ICPU_GENERAL_CTRL_CPU_BUSIF_SLEEP_DIS             BIT(11)
22 #define ICPU_GENERAL_CTRL_CPU_BUSIF_WERR_ENA              BIT(10)
23 #define ICPU_GENERAL_CTRL_CPU_8051_IROM_ENA               BIT(9)
24 #define ICPU_GENERAL_CTRL_CPU_MIPS_DIS                    BIT(8)
25 #define ICPU_GENERAL_CTRL_IF_MIIM_SLV_ENA                 BIT(7)
26 #define ICPU_GENERAL_CTRL_IF_PI_SLV_DONEPOL               BIT(6)
27 #define ICPU_GENERAL_CTRL_IF_PI_MST_ENA                   BIT(5)
28 #define ICPU_GENERAL_CTRL_IF_PI_SLV_ENA                   BIT(4)
29 #define ICPU_GENERAL_CTRL_IF_SI_MST_ENA                   BIT(3)
30 #define ICPU_GENERAL_CTRL_CPU_BE_ENA                      BIT(2)
31 #define ICPU_GENERAL_CTRL_CPU_DIS                         BIT(1)
32 #define ICPU_GENERAL_CTRL_BOOT_MODE_ENA                   BIT(0)
33 
34 #define ICPU_SPI_MST_CFG                                  0x3c
35 
36 #define ICPU_SPI_MST_CFG_FAST_READ_ENA                    BIT(10)
37 #define ICPU_SPI_MST_CFG_CS_DESELECT_TIME(x)              (((x) << 5) & GENMASK(9, 5))
38 #define ICPU_SPI_MST_CFG_CS_DESELECT_TIME_M               GENMASK(9, 5)
39 #define ICPU_SPI_MST_CFG_CS_DESELECT_TIME_X(x)            (((x) & GENMASK(9, 5)) >> 5)
40 #define ICPU_SPI_MST_CFG_CLK_DIV(x)                       ((x) & GENMASK(4, 0))
41 #define ICPU_SPI_MST_CFG_CLK_DIV_M                        GENMASK(4, 0)
42 
43 #define ICPU_SW_MODE                                      0x50
44 
45 #define ICPU_SW_MODE_SW_PIN_CTRL_MODE                     BIT(13)
46 #define ICPU_SW_MODE_SW_SPI_SCK                           BIT(12)
47 #define ICPU_SW_MODE_SW_SPI_SCK_OE                        BIT(11)
48 #define ICPU_SW_MODE_SW_SPI_SDO                           BIT(10)
49 #define ICPU_SW_MODE_SW_SPI_SDO_OE                        BIT(9)
50 #define ICPU_SW_MODE_SW_SPI_CS(x)                         (((x) << 5) & GENMASK(8, 5))
51 #define ICPU_SW_MODE_SW_SPI_CS_M                          GENMASK(8, 5)
52 #define ICPU_SW_MODE_SW_SPI_CS_X(x)                       (((x) & GENMASK(8, 5)) >> 5)
53 #define ICPU_SW_MODE_SW_SPI_CS_OE(x)                      (((x) << 1) & GENMASK(4, 1))
54 #define ICPU_SW_MODE_SW_SPI_CS_OE_M                       GENMASK(4, 1)
55 #define ICPU_SW_MODE_SW_SPI_CS_OE_X(x)                    (((x) & GENMASK(4, 1)) >> 1)
56 #define ICPU_SW_MODE_SW_SPI_SDI                           BIT(0)
57 
58 #define ICPU_INTR_ENA                                     0x84
59 
60 #define ICPU_DST_INTR_MAP(x)                              (0x94 + 0x4 * (x))
61 #define ICPU_DST_INTR_MAP_RSZ                             0x4
62 
63 #define ICPU_TIMER_TICK_DIV                               0xe0
64 
65 #define ICPU_TIMER_VALUE(x)                               (0xe4 + 0x4 * (x))
66 #define ICPU_TIMER_VALUE_RSZ                              0x2
67 
68 #define ICPU_TIMER_CTRL(x)                                (0xfc + 0x4 * (x))
69 #define ICPU_TIMER_CTRL_RSZ                               0x2
70 
71 #define ICPU_TIMER_CTRL_MAX_FREQ_ENA                      BIT(3)
72 #define ICPU_TIMER_CTRL_ONE_SHOT_ENA                      BIT(2)
73 #define ICPU_TIMER_CTRL_TIMER_ENA                         BIT(1)
74 #define ICPU_TIMER_CTRL_FORCE_RELOAD                      BIT(0)
75 
76 #define ICPU_MEMCTRL_CTRL                                 0x108
77 
78 #define ICPU_MEMCTRL_CTRL_PWR_DOWN                        BIT(3)
79 #define ICPU_MEMCTRL_CTRL_MDSET                           BIT(2)
80 #define ICPU_MEMCTRL_CTRL_STALL_REF_ENA                   BIT(1)
81 #define ICPU_MEMCTRL_CTRL_INITIALIZE                      BIT(0)
82 
83 #define ICPU_MEMCTRL_CFG                                  0x10c
84 
85 #define ICPU_MEMCTRL_CFG_DDR_512MBYTE_PLUS                BIT(16)
86 #define ICPU_MEMCTRL_CFG_DDR_ECC_ERR_ENA                  BIT(15)
87 #define ICPU_MEMCTRL_CFG_DDR_ECC_COR_ENA                  BIT(14)
88 #define ICPU_MEMCTRL_CFG_DDR_ECC_ENA                      BIT(13)
89 #define ICPU_MEMCTRL_CFG_DDR_WIDTH                        BIT(12)
90 #define ICPU_MEMCTRL_CFG_DDR_MODE                         BIT(11)
91 #define ICPU_MEMCTRL_CFG_BURST_SIZE                       BIT(10)
92 #define ICPU_MEMCTRL_CFG_BURST_LEN                        BIT(9)
93 #define ICPU_MEMCTRL_CFG_BANK_CNT                         BIT(8)
94 #define ICPU_MEMCTRL_CFG_MSB_ROW_ADDR(x)                  (((x) << 4) & GENMASK(7, 4))
95 #define ICPU_MEMCTRL_CFG_MSB_ROW_ADDR_M                   GENMASK(7, 4)
96 #define ICPU_MEMCTRL_CFG_MSB_ROW_ADDR_X(x)                (((x) & GENMASK(7, 4)) >> 4)
97 #define ICPU_MEMCTRL_CFG_MSB_COL_ADDR(x)                  ((x) & GENMASK(3, 0))
98 #define ICPU_MEMCTRL_CFG_MSB_COL_ADDR_M                   GENMASK(3, 0)
99 
100 #define ICPU_MEMCTRL_STAT                                 0x110
101 
102 #define ICPU_MEMCTRL_STAT_RDATA_MASKED                    BIT(5)
103 #define ICPU_MEMCTRL_STAT_RDATA_DUMMY                     BIT(4)
104 #define ICPU_MEMCTRL_STAT_RDATA_ECC_ERR                   BIT(3)
105 #define ICPU_MEMCTRL_STAT_RDATA_ECC_COR                   BIT(2)
106 #define ICPU_MEMCTRL_STAT_PWR_DOWN_ACK                    BIT(1)
107 #define ICPU_MEMCTRL_STAT_INIT_DONE                       BIT(0)
108 
109 #define ICPU_MEMCTRL_REF_PERIOD                           0x114
110 
111 #define ICPU_MEMCTRL_REF_PERIOD_MAX_PEND_REF(x)           (((x) << 16) & GENMASK(19, 16))
112 #define ICPU_MEMCTRL_REF_PERIOD_MAX_PEND_REF_M            GENMASK(19, 16)
113 #define ICPU_MEMCTRL_REF_PERIOD_MAX_PEND_REF_X(x)         (((x) & GENMASK(19, 16)) >> 16)
114 #define ICPU_MEMCTRL_REF_PERIOD_REF_PERIOD(x)             ((x) & GENMASK(15, 0))
115 #define ICPU_MEMCTRL_REF_PERIOD_REF_PERIOD_M              GENMASK(15, 0)
116 
117 #define ICPU_MEMCTRL_ZQCAL                                0x118
118 
119 #define ICPU_MEMCTRL_ZQCAL_ZQCAL_LONG                     BIT(1)
120 #define ICPU_MEMCTRL_ZQCAL_ZQCAL_SHORT                    BIT(0)
121 
122 #define ICPU_MEMCTRL_TIMING0                              0x11c
123 
124 #define ICPU_MEMCTRL_TIMING0_RD_TO_WR_DLY(x)              (((x) << 28) & GENMASK(31, 28))
125 #define ICPU_MEMCTRL_TIMING0_RD_TO_WR_DLY_M               GENMASK(31, 28)
126 #define ICPU_MEMCTRL_TIMING0_RD_TO_WR_DLY_X(x)            (((x) & GENMASK(31, 28)) >> 28)
127 #define ICPU_MEMCTRL_TIMING0_WR_CS_CHANGE_DLY(x)          (((x) << 24) & GENMASK(27, 24))
128 #define ICPU_MEMCTRL_TIMING0_WR_CS_CHANGE_DLY_M           GENMASK(27, 24)
129 #define ICPU_MEMCTRL_TIMING0_WR_CS_CHANGE_DLY_X(x)        (((x) & GENMASK(27, 24)) >> 24)
130 #define ICPU_MEMCTRL_TIMING0_RD_CS_CHANGE_DLY(x)          (((x) << 20) & GENMASK(23, 20))
131 #define ICPU_MEMCTRL_TIMING0_RD_CS_CHANGE_DLY_M           GENMASK(23, 20)
132 #define ICPU_MEMCTRL_TIMING0_RD_CS_CHANGE_DLY_X(x)        (((x) & GENMASK(23, 20)) >> 20)
133 #define ICPU_MEMCTRL_TIMING0_RAS_TO_PRECH_DLY(x)          (((x) << 16) & GENMASK(19, 16))
134 #define ICPU_MEMCTRL_TIMING0_RAS_TO_PRECH_DLY_M           GENMASK(19, 16)
135 #define ICPU_MEMCTRL_TIMING0_RAS_TO_PRECH_DLY_X(x)        (((x) & GENMASK(19, 16)) >> 16)
136 #define ICPU_MEMCTRL_TIMING0_WR_TO_PRECH_DLY(x)           (((x) << 12) & GENMASK(15, 12))
137 #define ICPU_MEMCTRL_TIMING0_WR_TO_PRECH_DLY_M            GENMASK(15, 12)
138 #define ICPU_MEMCTRL_TIMING0_WR_TO_PRECH_DLY_X(x)         (((x) & GENMASK(15, 12)) >> 12)
139 #define ICPU_MEMCTRL_TIMING0_RD_TO_PRECH_DLY(x)           (((x) << 8) & GENMASK(11, 8))
140 #define ICPU_MEMCTRL_TIMING0_RD_TO_PRECH_DLY_M            GENMASK(11, 8)
141 #define ICPU_MEMCTRL_TIMING0_RD_TO_PRECH_DLY_X(x)         (((x) & GENMASK(11, 8)) >> 8)
142 #define ICPU_MEMCTRL_TIMING0_WR_DATA_XFR_DLY(x)           (((x) << 4) & GENMASK(7, 4))
143 #define ICPU_MEMCTRL_TIMING0_WR_DATA_XFR_DLY_M            GENMASK(7, 4)
144 #define ICPU_MEMCTRL_TIMING0_WR_DATA_XFR_DLY_X(x)         (((x) & GENMASK(7, 4)) >> 4)
145 #define ICPU_MEMCTRL_TIMING0_RD_DATA_XFR_DLY(x)           ((x) & GENMASK(3, 0))
146 #define ICPU_MEMCTRL_TIMING0_RD_DATA_XFR_DLY_M            GENMASK(3, 0)
147 
148 #define ICPU_MEMCTRL_TIMING1                              0x120
149 
150 #define ICPU_MEMCTRL_TIMING1_RAS_TO_RAS_SAME_BANK_DLY(x)  (((x) << 24) & GENMASK(31, 24))
151 #define ICPU_MEMCTRL_TIMING1_RAS_TO_RAS_SAME_BANK_DLY_M   GENMASK(31, 24)
152 #define ICPU_MEMCTRL_TIMING1_RAS_TO_RAS_SAME_BANK_DLY_X(x) (((x) & GENMASK(31, 24)) >> 24)
153 #define ICPU_MEMCTRL_TIMING1_BANK8_FAW_DLY(x)             (((x) << 16) & GENMASK(23, 16))
154 #define ICPU_MEMCTRL_TIMING1_BANK8_FAW_DLY_M              GENMASK(23, 16)
155 #define ICPU_MEMCTRL_TIMING1_BANK8_FAW_DLY_X(x)           (((x) & GENMASK(23, 16)) >> 16)
156 #define ICPU_MEMCTRL_TIMING1_PRECH_TO_RAS_DLY(x)          (((x) << 12) & GENMASK(15, 12))
157 #define ICPU_MEMCTRL_TIMING1_PRECH_TO_RAS_DLY_M           GENMASK(15, 12)
158 #define ICPU_MEMCTRL_TIMING1_PRECH_TO_RAS_DLY_X(x)        (((x) & GENMASK(15, 12)) >> 12)
159 #define ICPU_MEMCTRL_TIMING1_RAS_TO_RAS_DLY(x)            (((x) << 8) & GENMASK(11, 8))
160 #define ICPU_MEMCTRL_TIMING1_RAS_TO_RAS_DLY_M             GENMASK(11, 8)
161 #define ICPU_MEMCTRL_TIMING1_RAS_TO_RAS_DLY_X(x)          (((x) & GENMASK(11, 8)) >> 8)
162 #define ICPU_MEMCTRL_TIMING1_RAS_TO_CAS_DLY(x)            (((x) << 4) & GENMASK(7, 4))
163 #define ICPU_MEMCTRL_TIMING1_RAS_TO_CAS_DLY_M             GENMASK(7, 4)
164 #define ICPU_MEMCTRL_TIMING1_RAS_TO_CAS_DLY_X(x)          (((x) & GENMASK(7, 4)) >> 4)
165 #define ICPU_MEMCTRL_TIMING1_WR_TO_RD_DLY(x)              ((x) & GENMASK(3, 0))
166 #define ICPU_MEMCTRL_TIMING1_WR_TO_RD_DLY_M               GENMASK(3, 0)
167 
168 #define ICPU_MEMCTRL_TIMING2                              0x124
169 
170 #define ICPU_MEMCTRL_TIMING2_PRECH_ALL_DLY(x)             (((x) << 28) & GENMASK(31, 28))
171 #define ICPU_MEMCTRL_TIMING2_PRECH_ALL_DLY_M              GENMASK(31, 28)
172 #define ICPU_MEMCTRL_TIMING2_PRECH_ALL_DLY_X(x)           (((x) & GENMASK(31, 28)) >> 28)
173 #define ICPU_MEMCTRL_TIMING2_MDSET_DLY(x)                 (((x) << 24) & GENMASK(27, 24))
174 #define ICPU_MEMCTRL_TIMING2_MDSET_DLY_M                  GENMASK(27, 24)
175 #define ICPU_MEMCTRL_TIMING2_MDSET_DLY_X(x)               (((x) & GENMASK(27, 24)) >> 24)
176 #define ICPU_MEMCTRL_TIMING2_REF_DLY(x)                   (((x) << 16) & GENMASK(23, 16))
177 #define ICPU_MEMCTRL_TIMING2_REF_DLY_M                    GENMASK(23, 16)
178 #define ICPU_MEMCTRL_TIMING2_REF_DLY_X(x)                 (((x) & GENMASK(23, 16)) >> 16)
179 #define ICPU_MEMCTRL_TIMING2_INIT_DLY(x)                  ((x) & GENMASK(15, 0))
180 #define ICPU_MEMCTRL_TIMING2_INIT_DLY_M                   GENMASK(15, 0)
181 
182 #define ICPU_MEMCTRL_TIMING3                              0x128
183 
184 #define ICPU_MEMCTRL_TIMING3_RMW_DLY(x)                   (((x) << 16) & GENMASK(19, 16))
185 #define ICPU_MEMCTRL_TIMING3_RMW_DLY_M                    GENMASK(19, 16)
186 #define ICPU_MEMCTRL_TIMING3_RMW_DLY_X(x)                 (((x) & GENMASK(19, 16)) >> 16)
187 #define ICPU_MEMCTRL_TIMING3_ODT_RD_DLY(x)                (((x) << 12) & GENMASK(15, 12))
188 #define ICPU_MEMCTRL_TIMING3_ODT_RD_DLY_M                 GENMASK(15, 12)
189 #define ICPU_MEMCTRL_TIMING3_ODT_RD_DLY_X(x)              (((x) & GENMASK(15, 12)) >> 12)
190 #define ICPU_MEMCTRL_TIMING3_ODT_WR_DLY(x)                (((x) << 8) & GENMASK(11, 8))
191 #define ICPU_MEMCTRL_TIMING3_ODT_WR_DLY_M                 GENMASK(11, 8)
192 #define ICPU_MEMCTRL_TIMING3_ODT_WR_DLY_X(x)              (((x) & GENMASK(11, 8)) >> 8)
193 #define ICPU_MEMCTRL_TIMING3_LOCAL_ODT_RD_DLY(x)          (((x) << 4) & GENMASK(7, 4))
194 #define ICPU_MEMCTRL_TIMING3_LOCAL_ODT_RD_DLY_M           GENMASK(7, 4)
195 #define ICPU_MEMCTRL_TIMING3_LOCAL_ODT_RD_DLY_X(x)        (((x) & GENMASK(7, 4)) >> 4)
196 #define ICPU_MEMCTRL_TIMING3_WR_TO_RD_CS_CHANGE_DLY(x)    ((x) & GENMASK(3, 0))
197 #define ICPU_MEMCTRL_TIMING3_WR_TO_RD_CS_CHANGE_DLY_M     GENMASK(3, 0)
198 
199 #define ICPU_MEMCTRL_TIMING4                              0x12c
200 
201 #define ICPU_MEMCTRL_TIMING4_ZQCAL_INIT_DLY(x)            (((x) << 20) & GENMASK(31, 20))
202 #define ICPU_MEMCTRL_TIMING4_ZQCAL_INIT_DLY_M             GENMASK(31, 20)
203 #define ICPU_MEMCTRL_TIMING4_ZQCAL_INIT_DLY_X(x)          (((x) & GENMASK(31, 20)) >> 20)
204 #define ICPU_MEMCTRL_TIMING4_ZQCAL_LONG_DLY(x)            (((x) << 8) & GENMASK(19, 8))
205 #define ICPU_MEMCTRL_TIMING4_ZQCAL_LONG_DLY_M             GENMASK(19, 8)
206 #define ICPU_MEMCTRL_TIMING4_ZQCAL_LONG_DLY_X(x)          (((x) & GENMASK(19, 8)) >> 8)
207 #define ICPU_MEMCTRL_TIMING4_ZQCAL_SHORT_DLY(x)           ((x) & GENMASK(7, 0))
208 #define ICPU_MEMCTRL_TIMING4_ZQCAL_SHORT_DLY_M            GENMASK(7, 0)
209 
210 #define ICPU_MEMCTRL_MR0_VAL                              0x130
211 
212 #define ICPU_MEMCTRL_MR1_VAL                              0x134
213 
214 #define ICPU_MEMCTRL_MR2_VAL                              0x138
215 
216 #define ICPU_MEMCTRL_MR3_VAL                              0x13c
217 
218 #define ICPU_MEMCTRL_TERMRES_CTRL                         0x140
219 
220 #define ICPU_MEMCTRL_TERMRES_CTRL_ODT_RD_EXT              BIT(11)
221 #define ICPU_MEMCTRL_TERMRES_CTRL_ODT_RD_ENA(x)           (((x) << 7) & GENMASK(10, 7))
222 #define ICPU_MEMCTRL_TERMRES_CTRL_ODT_RD_ENA_M            GENMASK(10, 7)
223 #define ICPU_MEMCTRL_TERMRES_CTRL_ODT_RD_ENA_X(x)         (((x) & GENMASK(10, 7)) >> 7)
224 #define ICPU_MEMCTRL_TERMRES_CTRL_ODT_WR_EXT              BIT(6)
225 #define ICPU_MEMCTRL_TERMRES_CTRL_ODT_WR_ENA(x)           (((x) << 2) & GENMASK(5, 2))
226 #define ICPU_MEMCTRL_TERMRES_CTRL_ODT_WR_ENA_M            GENMASK(5, 2)
227 #define ICPU_MEMCTRL_TERMRES_CTRL_ODT_WR_ENA_X(x)         (((x) & GENMASK(5, 2)) >> 2)
228 #define ICPU_MEMCTRL_TERMRES_CTRL_LOCAL_ODT_RD_EXT        BIT(1)
229 #define ICPU_MEMCTRL_TERMRES_CTRL_LOCAL_ODT_RD_ENA        BIT(0)
230 
231 #define ICPU_MEMCTRL_DFT                                  0x144
232 
233 #define ICPU_MEMCTRL_DFT_DDRDFT_LBW                       BIT(7)
234 #define ICPU_MEMCTRL_DFT_DDRDFT_GATE_ENA                  BIT(6)
235 #define ICPU_MEMCTRL_DFT_DDRDFT_TERM_ENA                  BIT(5)
236 #define ICPU_MEMCTRL_DFT_DDRDFT_A10                       BIT(4)
237 #define ICPU_MEMCTRL_DFT_DDRDFT_STAT                      BIT(3)
238 #define ICPU_MEMCTRL_DFT_DDRDFT_MODE(x)                   (((x) << 1) & GENMASK(2, 1))
239 #define ICPU_MEMCTRL_DFT_DDRDFT_MODE_M                    GENMASK(2, 1)
240 #define ICPU_MEMCTRL_DFT_DDRDFT_MODE_X(x)                 (((x) & GENMASK(2, 1)) >> 1)
241 #define ICPU_MEMCTRL_DFT_DDRDFT_ENA                       BIT(0)
242 
243 #define ICPU_MEMCTRL_DQS_DLY(x)                           (0x148 + 0x4 * (x))
244 #define ICPU_MEMCTRL_DQS_DLY_RSZ                          0x2
245 
246 #define ICPU_MEMCTRL_DQS_DLY_TRAIN_DQ_ENA                 BIT(11)
247 #define ICPU_MEMCTRL_DQS_DLY_DQS_DLY_TRM1(x)              (((x) << 8) & GENMASK(10, 8))
248 #define ICPU_MEMCTRL_DQS_DLY_DQS_DLY_TRM1_M               GENMASK(10, 8)
249 #define ICPU_MEMCTRL_DQS_DLY_DQS_DLY_TRM1_X(x)            (((x) & GENMASK(10, 8)) >> 8)
250 #define ICPU_MEMCTRL_DQS_DLY_DQS_DLY_TRM0(x)              (((x) << 5) & GENMASK(7, 5))
251 #define ICPU_MEMCTRL_DQS_DLY_DQS_DLY_TRM0_M               GENMASK(7, 5)
252 #define ICPU_MEMCTRL_DQS_DLY_DQS_DLY_TRM0_X(x)            (((x) & GENMASK(7, 5)) >> 5)
253 #define ICPU_MEMCTRL_DQS_DLY_DQS_DLY(x)                   ((x) & GENMASK(4, 0))
254 #define ICPU_MEMCTRL_DQS_DLY_DQS_DLY_M                    GENMASK(4, 0)
255 
256 #define ICPU_MEMCTRL_DQS_AUTO                             0x150
257 #define ICPU_MEMCTRL_DQS_AUTO_RSZ                         0x2
258 
259 #define ICPU_MEMCTRL_DQS_AUTO_DQS_DRIFT(x)                (((x) << 6) & GENMASK(7, 6))
260 #define ICPU_MEMCTRL_DQS_AUTO_DQS_DRIFT_M                 GENMASK(7, 6)
261 #define ICPU_MEMCTRL_DQS_AUTO_DQS_DRIFT_X(x)              (((x) & GENMASK(7, 6)) >> 6)
262 #define ICPU_MEMCTRL_DQS_AUTO_DQS_OVERFLOW                BIT(5)
263 #define ICPU_MEMCTRL_DQS_AUTO_DQS_UNDERFLOW               BIT(4)
264 #define ICPU_MEMCTRL_DQS_AUTO_DQS_AUTO_SRC                BIT(3)
265 #define ICPU_MEMCTRL_DQS_AUTO_DQS_AUTO_UP                 BIT(2)
266 #define ICPU_MEMCTRL_DQS_AUTO_DQS_AUTO_DOWN               BIT(1)
267 #define ICPU_MEMCTRL_DQS_AUTO_DQS_AUTO_ENA                BIT(0)
268 
269 #define ICPU_MEMPHY_CFG                                   0x158
270 
271 #define ICPU_MEMPHY_CFG_PHY_FLUSH_DIS                     BIT(10)
272 #define ICPU_MEMPHY_CFG_PHY_RD_ADJ_DIS                    BIT(9)
273 #define ICPU_MEMPHY_CFG_PHY_DQS_EXT                       BIT(8)
274 #define ICPU_MEMPHY_CFG_PHY_FIFO_RST                      BIT(7)
275 #define ICPU_MEMPHY_CFG_PHY_DLL_BL_RST                    BIT(6)
276 #define ICPU_MEMPHY_CFG_PHY_DLL_CL_RST                    BIT(5)
277 #define ICPU_MEMPHY_CFG_PHY_ODT_OE                        BIT(4)
278 #define ICPU_MEMPHY_CFG_PHY_CK_OE                         BIT(3)
279 #define ICPU_MEMPHY_CFG_PHY_CL_OE                         BIT(2)
280 #define ICPU_MEMPHY_CFG_PHY_SSTL_ENA                      BIT(1)
281 #define ICPU_MEMPHY_CFG_PHY_RST                           BIT(0)
282 
283 #define ICPU_MEMPHY_ZCAL                                  0x180
284 
285 #define ICPU_MEMPHY_ZCAL_ZCAL_CLK_SEL                     BIT(9)
286 #define ICPU_MEMPHY_ZCAL_ZCAL_PROG_ODT(x)                 (((x) << 5) & GENMASK(8, 5))
287 #define ICPU_MEMPHY_ZCAL_ZCAL_PROG_ODT_M                  GENMASK(8, 5)
288 #define ICPU_MEMPHY_ZCAL_ZCAL_PROG_ODT_X(x)               (((x) & GENMASK(8, 5)) >> 5)
289 #define ICPU_MEMPHY_ZCAL_ZCAL_PROG(x)                     (((x) << 1) & GENMASK(4, 1))
290 #define ICPU_MEMPHY_ZCAL_ZCAL_PROG_M                      GENMASK(4, 1)
291 #define ICPU_MEMPHY_ZCAL_ZCAL_PROG_X(x)                   (((x) & GENMASK(4, 1)) >> 1)
292 #define ICPU_MEMPHY_ZCAL_ZCAL_ENA                         BIT(0)
293 
294 #define ICPU_MEMPHY_ZCAL_STAT                             0x184
295 
296 #define ICPU_MEMPHY_ZCAL_STAT_ZCAL_ZCTRL(x)               (((x) << 12) & GENMASK(31, 12))
297 #define ICPU_MEMPHY_ZCAL_STAT_ZCAL_ZCTRL_M                GENMASK(31, 12)
298 #define ICPU_MEMPHY_ZCAL_STAT_ZCAL_ZCTRL_X(x)             (((x) & GENMASK(31, 12)) >> 12)
299 #define ICPU_MEMPHY_ZCAL_STAT_ZCAL_STAT_ODTPU(x)          (((x) << 8) & GENMASK(9, 8))
300 #define ICPU_MEMPHY_ZCAL_STAT_ZCAL_STAT_ODTPU_M           GENMASK(9, 8)
301 #define ICPU_MEMPHY_ZCAL_STAT_ZCAL_STAT_ODTPU_X(x)        (((x) & GENMASK(9, 8)) >> 8)
302 #define ICPU_MEMPHY_ZCAL_STAT_ZCAL_STAT_ODTPD(x)          (((x) << 6) & GENMASK(7, 6))
303 #define ICPU_MEMPHY_ZCAL_STAT_ZCAL_STAT_ODTPD_M           GENMASK(7, 6)
304 #define ICPU_MEMPHY_ZCAL_STAT_ZCAL_STAT_ODTPD_X(x)        (((x) & GENMASK(7, 6)) >> 6)
305 #define ICPU_MEMPHY_ZCAL_STAT_ZCAL_STAT_PU(x)             (((x) << 4) & GENMASK(5, 4))
306 #define ICPU_MEMPHY_ZCAL_STAT_ZCAL_STAT_PU_M              GENMASK(5, 4)
307 #define ICPU_MEMPHY_ZCAL_STAT_ZCAL_STAT_PU_X(x)           (((x) & GENMASK(5, 4)) >> 4)
308 #define ICPU_MEMPHY_ZCAL_STAT_ZCAL_STAT_PD(x)             (((x) << 2) & GENMASK(3, 2))
309 #define ICPU_MEMPHY_ZCAL_STAT_ZCAL_STAT_PD_M              GENMASK(3, 2)
310 #define ICPU_MEMPHY_ZCAL_STAT_ZCAL_STAT_PD_X(x)           (((x) & GENMASK(3, 2)) >> 2)
311 #define ICPU_MEMPHY_ZCAL_STAT_ZCAL_ERR                    BIT(1)
312 #define ICPU_MEMPHY_ZCAL_STAT_ZCAL_DONE                   BIT(0)
313 
314 #endif
315