1 /* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
2 /*
3  * Copyright (c) 2018 Microsemi Corporation
4  */
5 
6 #ifndef _MSCC_OCELOT_DEVCPU_GCB_MIIM_REGS_H_
7 #define _MSCC_OCELOT_DEVCPU_GCB_MIIM_REGS_H_
8 
9 #define MIIM_MII_STATUS(gi) (0x9c + (gi * 36))
10 #define MIIM_MII_CMD(gi)    (0xa4 + (gi * 36))
11 #define MIIM_MII_DATA(gi)   (0xa8 + (gi * 36))
12 
13 #define MSCC_F_MII_STATUS_MIIM_STAT_BUSY(x)   ((x) ? BIT(3) : 0)
14 
15 #define MSCC_F_MII_CMD_MIIM_CMD_VLD(x)        ((x) ? BIT(31) : 0)
16 #define MSCC_F_MII_CMD_MIIM_CMD_PHYAD(x)      (GENMASK(29, 25) & ((x) << 25))
17 #define MSCC_F_MII_CMD_MIIM_CMD_REGAD(x)      (GENMASK(24, 20) & ((x) << 20))
18 #define MSCC_F_MII_CMD_MIIM_CMD_WRDATA(x)     (GENMASK(19, 4) & ((x) << 4))
19 #define MSCC_F_MII_CMD_MIIM_CMD_OPR_FIELD(x)  (GENMASK(2, 1) & ((x) << 1))
20 #define MSCC_F_MII_CMD_MIIM_CMD_SCAN(x)       ((x) ? BIT(0) : 0)
21 
22 #define MSCC_M_MII_DATA_MIIM_DATA_SUCCESS     GENMASK(17, 16)
23 #define MSCC_X_MII_DATA_MIIM_DATA_RDDATA(x)   (((x) >> 0) & GENMASK(15, 0))
24 
25 #endif
26