1 /* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ 2 /* 3 * Copyright (c) 2018 Microsemi Corporation 4 */ 5 6 #ifndef __ASM_MACH_COMMON_H 7 #define __ASM_MACH_COMMON_H 8 9 #if defined(CONFIG_SOC_OCELOT) 10 #include <mach/ocelot/ocelot.h> 11 #include <mach/ocelot/ocelot_devcpu_gcb.h> 12 #include <mach/ocelot/ocelot_icpu_cfg.h> 13 #else 14 #error Unsupported platform 15 #endif 16 17 #define MSCC_DDR_TO 0x20000000 /* DDR RAM base offset */ 18 #define MSCC_MEMCTL1_TO 0x40000000 /* SPI/PI base offset */ 19 #define MSCC_MEMCTL2_TO 0x50000000 /* SPI/PI base offset */ 20 #define MSCC_FLASH_TO MSCC_MEMCTL1_TO /* Flash base offset */ 21 22 #define VCOREIII_TIMER_DIVIDER 25 /* Clock tick ~ 0.1 us */ 23 24 #endif /* __ASM_MACH_COMMON_H */ 25