1 /* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ 2 /* 3 * Copyright (c) 2018 Microsemi Corporation 4 */ 5 6 #ifndef __ASM_MACH_COMMON_H 7 #define __ASM_MACH_COMMON_H 8 9 #if defined(CONFIG_SOC_OCELOT) 10 #include <mach/ocelot/ocelot.h> 11 #include <mach/ocelot/ocelot_devcpu_gcb.h> 12 #include <mach/ocelot/ocelot_devcpu_gcb_miim_regs.h> 13 #include <mach/ocelot/ocelot_icpu_cfg.h> 14 #elif defined(CONFIG_SOC_LUTON) 15 #include <mach/luton/luton.h> 16 #include <mach/luton/luton_devcpu_gcb.h> 17 #include <mach/luton/luton_devcpu_gcb_miim_regs.h> 18 #include <mach/luton/luton_icpu_cfg.h> 19 #elif defined(CONFIG_SOC_JR2) 20 #include <mach/jr2/jr2.h> 21 #include <mach/jr2/jr2_devcpu_gcb.h> 22 #include <mach/jr2/jr2_devcpu_gcb_miim_regs.h> 23 #include <mach/jr2/jr2_icpu_cfg.h> 24 #elif defined(CONFIG_SOC_SERVALT) 25 #include <mach/servalt/servalt.h> 26 #include <mach/servalt/servalt_devcpu_gcb.h> 27 #include <mach/servalt/servalt_devcpu_gcb_miim_regs.h> 28 #include <mach/servalt/servalt_icpu_cfg.h> 29 #elif defined(CONFIG_SOC_SERVAL) 30 #include <mach/serval/serval.h> 31 #include <mach/serval/serval_devcpu_gcb.h> 32 #include <mach/serval/serval_devcpu_gcb_miim_regs.h> 33 #include <mach/serval/serval_icpu_cfg.h> 34 #else 35 #error Unsupported platform 36 #endif 37 38 #define MSCC_DDR_TO 0x20000000 /* DDR RAM base offset */ 39 #define MSCC_MEMCTL1_TO 0x40000000 /* SPI/PI base offset */ 40 #define MSCC_MEMCTL2_TO 0x50000000 /* SPI/PI base offset */ 41 #define MSCC_FLASH_TO MSCC_MEMCTL1_TO /* Flash base offset */ 42 43 #define VCOREIII_TIMER_DIVIDER 25 /* Clock tick ~ 0.1 us */ 44 45 /* Common utility functions */ 46 47 /* 48 * Perform a number of NOP instructions, blocks of 8 instructions. 49 * The (inlined) function will not affect cache or processor state. 50 */ 51 static inline void mscc_vcoreiii_nop_delay(int delay) 52 { 53 while (delay > 0) { 54 #define DELAY_8_NOPS() asm volatile("nop; nop; nop; nop; nop; nop; nop; nop;") 55 switch (delay) { 56 case 8: 57 DELAY_8_NOPS(); 58 /* fallthrough */ 59 case 7: 60 DELAY_8_NOPS(); 61 /* fallthrough */ 62 case 6: 63 DELAY_8_NOPS(); 64 /* fallthrough */ 65 case 5: 66 DELAY_8_NOPS(); 67 /* fallthrough */ 68 case 4: 69 DELAY_8_NOPS(); 70 /* fallthrough */ 71 case 3: 72 DELAY_8_NOPS(); 73 /* fallthrough */ 74 case 2: 75 DELAY_8_NOPS(); 76 /* fallthrough */ 77 case 1: 78 DELAY_8_NOPS(); 79 } 80 delay -= 8; 81 #undef DELAY_8_NOPS 82 } 83 } 84 85 int mscc_phy_rd_wr(u8 read, 86 u32 miim_controller, 87 u8 miim_addr, 88 u8 addr, 89 u16 *value); 90 91 int mscc_phy_rd(u32 miim_controller, 92 u8 miim_addr, 93 u8 addr, 94 u16 *value); 95 96 int mscc_phy_wr(u32 miim_controller, 97 u8 miim_addr, 98 u8 addr, 99 u16 value); 100 101 void mscc_gpio_set_alternate(int gpio, int mode); 102 103 #endif /* __ASM_MACH_COMMON_H */ 104