1 /* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ 2 /* 3 * Copyright (c) 2018 Microsemi Corporation 4 */ 5 6 #ifndef __ASM_MACH_COMMON_H 7 #define __ASM_MACH_COMMON_H 8 9 #if defined(CONFIG_SOC_OCELOT) 10 #include <mach/ocelot/ocelot.h> 11 #include <mach/ocelot/ocelot_devcpu_gcb.h> 12 #include <mach/ocelot/ocelot_devcpu_gcb_miim_regs.h> 13 #include <mach/ocelot/ocelot_icpu_cfg.h> 14 #elif defined(CONFIG_SOC_LUTON) 15 #include <mach/luton/luton.h> 16 #include <mach/luton/luton_devcpu_gcb.h> 17 #include <mach/luton/luton_devcpu_gcb_miim_regs.h> 18 #include <mach/luton/luton_icpu_cfg.h> 19 #else 20 #error Unsupported platform 21 #endif 22 23 #define MSCC_DDR_TO 0x20000000 /* DDR RAM base offset */ 24 #define MSCC_MEMCTL1_TO 0x40000000 /* SPI/PI base offset */ 25 #define MSCC_MEMCTL2_TO 0x50000000 /* SPI/PI base offset */ 26 #define MSCC_FLASH_TO MSCC_MEMCTL1_TO /* Flash base offset */ 27 28 #define VCOREIII_TIMER_DIVIDER 25 /* Clock tick ~ 0.1 us */ 29 30 /* Common utility functions */ 31 32 int mscc_phy_rd_wr(u8 read, 33 u32 miim_controller, 34 u8 miim_addr, 35 u8 addr, 36 u16 *value); 37 38 int mscc_phy_rd(u32 miim_controller, 39 u8 miim_addr, 40 u8 addr, 41 u16 *value); 42 43 int mscc_phy_wr(u32 miim_controller, 44 u8 miim_addr, 45 u8 addr, 46 u16 value); 47 48 #endif /* __ASM_MACH_COMMON_H */ 49