1*e58031acSLars Povlsen // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2*e58031acSLars Povlsen /* 3*e58031acSLars Povlsen * Copyright (c) 2018 Microsemi Corporation 4*e58031acSLars Povlsen */ 5*e58031acSLars Povlsen 6*e58031acSLars Povlsen #include <common.h> 7*e58031acSLars Povlsen #include <asm/io.h> 8*e58031acSLars Povlsen mscc_gpio_set_alternate(int gpio,int mode)9*e58031acSLars Povlsenvoid mscc_gpio_set_alternate(int gpio, int mode) 10*e58031acSLars Povlsen { 11*e58031acSLars Povlsen u32 mask = BIT(gpio); 12*e58031acSLars Povlsen u32 val0, val1; 13*e58031acSLars Povlsen 14*e58031acSLars Povlsen val0 = readl(BASE_DEVCPU_GCB + GPIO_ALT(0)); 15*e58031acSLars Povlsen val1 = readl(BASE_DEVCPU_GCB + GPIO_ALT(1)); 16*e58031acSLars Povlsen 17*e58031acSLars Povlsen if (mode == 1) { 18*e58031acSLars Povlsen val0 |= mask; 19*e58031acSLars Povlsen val1 &= ~mask; 20*e58031acSLars Povlsen } else if (mode == 2) { 21*e58031acSLars Povlsen val0 &= ~mask; 22*e58031acSLars Povlsen val1 |= mask; 23*e58031acSLars Povlsen } else if (mode == 3) { 24*e58031acSLars Povlsen val0 |= mask; 25*e58031acSLars Povlsen val1 |= mask; 26*e58031acSLars Povlsen } else { 27*e58031acSLars Povlsen val0 &= ~mask; 28*e58031acSLars Povlsen val1 &= ~mask; 29*e58031acSLars Povlsen } 30*e58031acSLars Povlsen 31*e58031acSLars Povlsen writel(val0, BASE_DEVCPU_GCB + GPIO_ALT(0)); 32*e58031acSLars Povlsen writel(val1, BASE_DEVCPU_GCB + GPIO_ALT(1)); 33*e58031acSLars Povlsen } 34